Hitachi H8S/2627, Руководство по оборудованию

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Rev. 1.0, 09/03, page 246 of 568
Bit
Bit Name Initial
Value
R/W
Description
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Select 2 to 0
The input clock can be selected from three clocks
divided from the system clock (
φ
). When use of an
external clock is selected, three types of count can
be selected: at the rising edge, the falling edge, and
both rising and falling edges.
000: Clock input disabled
001:
φ
/8 internal clock source, counted on the falling
edge
010:
φ
/64 internal clock source, counted on the falling
edge
011:
φ
/8192 internal clock source, counted on the
falling edge
100: For channel 0: Counted on TCNT1 overflow
signal
*
For channel 1: Counted on TCNT0 overflow signal *
For channel 2: Counted on TCNT3 overflow signal *
For channel 3: Counted on TCNT2 overflow signal *
101: External clock source, counted at rising edge
110: External clock source, counted at falling edge
111: External clock source, counted at both rising
and falling edges
Note:
*
If the count input of channel 0 (channel 2) is the TCNT1 (TCNT3) overflow signal and that of
channel 1 (channel 3) is the TCNT1 (TCNT3) compare-match signal, no incrementing clock
will be generated. Do not use this setting.