Rev. 1.0, 09/02, page 494 of 568
22.1
Register Addresses (Address Order)
The data-bus width column indicates the number of bits. The access-state column shows the
number of states of the selected basic clock that is required for access to the register.
Register Name
Abbreviation
Number
of Bits
Address
*
Module
Data
Width
Access
State
Master control register
MCR
8
H
′
F800 HCAN 16
4
General status register
GSR
8
H
′
F801 HCAN 16
4
Bit configuration register
BCR
16
H
′
F802 HCAN 16
4
Mailbox configuration register
MBCR
16
H
′
F804 HCAN 16
4
Transmit wait register
TXPR
16
H
′
F806 HCAN 16
4
Transmit wait cancel register
TXCR
16
H
′
F808 HCAN 16
4
Transmit acknowledge register
TXACK
16
H
′
F80A HCAN 16
4
Abort acknowledge register
ABACK
16
H
′
F80C HCAN 16
4
Receive complete register
RXPR
16
H
′
F80E HCAN 16
4
Remote request register
RFPR
16
H
′
F810 HCAN 16
4
Interrupt register
IRR
16
H
′
F812 HCAN 16
4
Mailbox interrupt mask register
MBIMR
16
H
′
F814 HCAN 16
4
Interrupt mask register
IMR
16
H
′
F816 HCAN 16
4
Receive error counter
REC
8
H
′
F818 HCAN 16
4
Transmit error counter
TEC
8
H
′
F819 HCAN 16
4
Unread message status register
UMSR
16
H
′
F81A HCAN 16
4
Local acceptance filter mask L
LAFML
16
H
′
F81C HCAN 16
4
Local acceptance filter mask H
LAFMH
16
H
′
F81E HCAN 16
4
Message control 0[1]
MC0[1]
8
H
′
F820 HCAN 16
4
Message control 0[2]
MC0[2]
8
H
′
F821 HCAN 16
4
Message control 0[3]
MC0[3]
8
H
′
F822 HCAN 16
4
Message control 0[4]
MC0[4]
8
H
′
F823 HCAN 16
4
Message control 0[5]
MC0[5]
8
H
′
F824 HCAN 16
4
Message control 0[6]
MC0[6]
8
H
′
F825 HCAN 16
4
Message control 0[7]
MC0[7]
8
H
′
F826 HCAN 16
4
Message control 0[8]
MC0[8]
8
H
′
F827 HCAN 16
4
Message control 1[1]
MC1[1]
8
H
′
F828 HCAN 16
4
Содержание H8S/2627
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