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12.4 Operation
12.4.1 Overview
Figure 12.2 shows a block diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR and NDER are set to 1. An initial output value is determined by its
corresponding PODR initial setting. When the compare match event specified by PCR occurs, the
corresponding NDR bit contents are transferred to PODR to update the output values.
The sequential output of up to 8 bits of data is possible by writing new output data to NDR before
the next compare match.
Output trigger signal
Pulse output pin
Internal data bus
Normal output/inverted output
C
PODR
Q
D
NDER
Q
NDR
Q
D
DDR
Figure 12.2 PPG Output Operation
Содержание H8S/2627
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