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clock from the pattern generator), or extract the clock signal from the incoming
data (CDR mode).
CDR mode does not work for all kinds of data patterns. For example, if the device
under test sends only blocks of ones and zeros, there are no transitions in the data
stream and the Serial BERT cannot recover the clock.
Also, if you are testing bursts, there are some special considerations for setting
up CDR. See the following sections for details.
How does Clock Data Recovery Work?
In CDR mode, the CDR has to recover the clock from the incoming data. To do this,
the hardware has to decide whether the voltage at the input connector is a logical
'1' or '0' and then recover the clock from the detected transitions.
Clock Data Recovery (CDR) is a special kind of Phase Locked Loop (PLL), which
recovers clock signal from of a data stream. It is a regulatory loop, which
synchronizes the local oscillator with an external reference, in this case the
incoming data stream.
Phase Locked Loop
A PLL has three parts: a phase detector, a loop filter, and a voltage controlled
oscillator (VCO). The phase detector has two inputs, and one output, which is
proportional to the phase difference of the inputs. The loop filter is a low pass filter
which attenuates the higher frequencies from the output of the phase detector.
The VCO is an adjustable oscillator which changes the output frequency depending
on its input voltage. The diagram below shows a simple PLL.
One of the most important characteristics of a PLL is its loop transfer function.The
loop bandwidth is defined as the integrated magnitude of the PLL’s frequency
transfer function over the entire frequency spectrum. The loop bandwidth describes
how the regulatory loop tracks the VCO to a sine wave FM modulated input signal.
Above the bandwidth the loop cannot track such a modulation completely, and
thus, the response to the modulation is attenuated.
The other loop parameter is peaking. This describes how much a modulation is
exaggerated (mostly close to the loop bandwidth).
5
Setting up the Error Detector
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Agilent J-BERT N4903B High-Performance Serial BERT
Содержание J-BERT N4903B
Страница 1: ...S Agilent J BERT N4903B High Performance Serial BERT User Guide s Agilent Technologies ...
Страница 10: ...10 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 36: ...1 Planning the Test 36 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 60: ...2 Setting up External Instrument s 60 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 120: ...3 Setting up Patterns 120 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 360: ...6 Advanced Analysis 360 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 468: ...8 Jitter Tolerance Tests 468 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 486: ... Input Timing Setup 2 Input Timing Setup 3 9 Solving Problems 486 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 487: ... Input Timing Setup 4 Input Timing Setup 5 Solving Problems 9 Agilent J BERT N4903B High Performance Serial BERT 487 ...
Страница 524: ...9 Solving Problems 524 Agilent J BERT N4903B High Performance Serial BERT ...
Страница 566: ...10 Customizing the Instrument 566 Agilent J BERT N4903B High Performance Serial BERT ...