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Virtex-5 FPGA User Guide
353
UG190 (v5.0) June 19, 2009
Chapter 8
Advanced SelectIO Logic Resources
Introduction
The I/O functionality in Virtex-5 FPGAs is described in
through
this user guide.
•
covers the electrical characteristics of input receivers and output drivers,
and their compliance with many industry standards.
•
describes the register structures dedicated for sending and receiving SDR
or DDR data.
•
This chapter covers additional resources:
♦
Input serial-to-parallel converters (ISERDES) and output parallel-to-serial
converters (OSERDES) support very fast I/O data rates, and allow the internal
logic to run up to 10 times slower than the I/O.
♦
The Bitslip submodule can re-align data to word boundaries, detected with the
help of a training pattern.
Input Serial-to-Parallel Logic Resources (ISERDES)
The ISERDES in Virtex-5 FPGAs is a dedicated serial-to-parallel converter with specific
clocking and logic features designed to facilitate the implementation of high-speed source-
synchronous applications. The ISERDES avoids the additional timing complexities
encountered when designing deserializers in the FPGA fabric.
ISERDES features include:
•
Dedicated Deserializer/Serial-to-Parallel Converter
The ISERDES deserializer enables high-speed data transfer without requiring the
FPGA fabric to match the input data frequency. This converter supports both single
data rate (SDR) and double data rate (DDR) modes. In SDR mode, the serial-to-parallel
converter creates a 2-, 3-, 4-, 5-, 6-, 7-, or 8-bit wide parallel word. In DDR mode, the
serial-to-parallel converter creates a 4-, 6-, 8-, or 10-bit-wide parallel word.
•
Bitslip Submodule
The Bitslip submodule allows designers to reorder the sequence of the parallel data
stream going into the FPGA fabric. This can be used for training source-synchronous
interfaces that include a training pattern.
•
Dedicated Support for Strobe-based Memory Interfaces
ISERDES contains dedicated circuitry (including the OCLK input pin) to handle the
strobe-to-FPGA clock domain crossover entirely within the ISERDES block. This
allows for higher performance and a simplified implementation.
Summary of Contents for Virtex-5 FPGA ML561
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Page 8: ...Virtex 5 FPGA User Guide www xilinx com UG190 v5 0 June 19 2009 ...
Page 20: ...20 www xilinx com Virtex 5 FPGA User Guide UG190 v5 0 June 19 2009 ...
Page 24: ...24 www xilinx com Virtex 5 FPGA User Guide UG190 v5 0 June 19 2009 Preface About This Guide ...
Page 172: ...172 www xilinx com Virtex 5 FPGA User Guide UG190 v5 0 June 19 2009 Chapter 4 Block RAM ...