General Lists
Name
Description
Logics.LE9.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE9.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE9.Reset Latch-I State of the module input: Reset Signal for the Latching
Logics.LE10.Gate Out
Signal: Output of the logic gate
Logics.LE10.Timer Out
Signal: Timer Output
Logics.LE10.Out
Signal: Latched Output (Q)
Logics.LE10.Out inverted Signal: Negated Latched Output (Q NOT)
Logics.LE10.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE10.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE10.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE10.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE10.Reset Latch-
I
State of the module input: Reset Signal for the Latching
Logics.LE11.Gate Out
Signal: Output of the logic gate
Logics.LE11.Timer Out
Signal: Timer Output
Logics.LE11.Out
Signal: Latched Output (Q)
Logics.LE11.Out inverted Signal: Negated Latched Output (Q NOT)
Logics.LE11.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE11.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE11.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE11.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE11.Reset Latch-
I
State of the module input: Reset Signal for the Latching
Logics.LE12.Gate Out
Signal: Output of the logic gate
Logics.LE12.Timer Out
Signal: Timer Output
Logics.LE12.Out
Signal: Latched Output (Q)
Logics.LE12.Out inverted Signal: Negated Latched Output (Q NOT)
Logics.LE12.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE12.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE12.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE12.Gate In4-I
State of the module input: Assignment of the Input Signal
Logics.LE12.Reset Latch-
I
State of the module input: Reset Signal for the Latching
Logics.LE13.Gate Out
Signal: Output of the logic gate
Logics.LE13.Timer Out
Signal: Timer Output
Logics.LE13.Out
Signal: Latched Output (Q)
Logics.LE13.Out inverted Signal: Negated Latched Output (Q NOT)
Logics.LE13.Gate In1-I
State of the module input: Assignment of the Input Signal
Logics.LE13.Gate In2-I
State of the module input: Assignment of the Input Signal
Logics.LE13.Gate In3-I
State of the module input: Assignment of the Input Signal
Logics.LE13.Gate In4-I
State of the module input: Assignment of the Input Signal
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MRI4
DOK-HB-MRI4-2E
Summary of Contents for highprotec MRI4
Page 1: ...Manual Feeder Protection MRI4 Software Version 3 4 a DOK HB MRI4 2E Revision C English...
Page 43: ...Installation and Connection 43 MRI4 DOK HB MRI4 2E...
Page 46: ...Installation and Connection Ensure the correct tightening torques 46 MRI4 DOK HB MRI4 2E...
Page 69: ...Navigation Operation Navigation Operation 69 MRI4 DOK HB MRI4 2E 1 2 3 5 7 6 8 10 9...
Page 353: ...Device Parameters 353 MRI4 DOK HB MRI4 2E...
Page 373: ...373 MRI4 DOK HB MRI4 2E...