4-27
4 Understanding Programming
CP2E CPU Unit Software User’s Manual(W614)
4-6 In
de
x
Register
s
4
4-6-2 U
s
ing Inde
x Registers
• Instructions for Direct Addressing of Index Registers:
BINARY ADD (+L), BINARY SUBTRACT (
−
L), DOUBLE INCREMENT BINARY (++L),
DOUBLE DECREMENT BINARY (
−−
L)
The example given above shows how an Index Register in a program loop can replace a long series of
instructions. In this case, instruction A is repeated n+1 times to perform some operation such as read-
ing and comparing a table of values.
Precautions for Correct Use
Precautions for Correct Use
The following instructions are executed even when the input conditions are OFF. Therefore,
when indirect memory addresses are specified using auto-incrementing or auto-decrementing
(,IR+ or ,IR-) in an operand of any of these instructions, the value in the Index Register (IR) is
refreshed each cycle regardless of the input condition (increases or decreases one every cycle).
This must be considered when writing a program.
The following ladder programming examples show how the index registers are treated.
Example 1
Ladder Program:
LD P_Off
OUT, IR0+
Operation: When the PLC memory address CIO 0.1
3
is stored in IR0.
The input condition is OFF (P_Off is the Always OFF Flag), so the OUT instruction sets CIO 0.1
3
,
which is indirectly addressed by IR0, to OFF. The OUT instruction is executed, so IR0 is incre-
mented. As a result, the PLC memory address CIO 0.14, which was incremented by +1 in the
IR0, is stored. Therefore, in the following cycle the OUT instruction turns OFF CIO 0.14.
Example 2
Ladder Program:
LD P_Off
SET, IR0+
Operation: When the PLC memory address CIO 0.1
3
is stored in IR0.
Classification
Instructions
Sequence input instructions
LD, LD NOT, AND, AND NOT, OR, OR NOT, LD TST, LD TSTN, AND
TST, AND TSTN, OR TST, OR TSTN
Sequence output instructions
OUT, OUT NOT, DIFU, DIFD
Sequence control instructions
JMP, FOR
Timer and counter instructions
TIM/TIMX(550), TIMH(015)/TIMHX(551), TMHH(540)/TMHHX(552),
TTIM(0
8
7)/TTIMX(555), TIML(542)/TIMLX(55
3
),
MTIM(5
33
)/MTIMX(554), CNT/CNTX(546),
CNTR(012)/CNTRX(54
8
)
Comparison instructions
Symbol comparison instructions (LD, AND, OR =, etc.)
Single-precision floating-point
math instructions
Single-precision floating-point data comparison (LD, AND, OR = F,
etc.)
Instruction A m
Instruction A m+1
Instruction A m+n
MO
V
R(560) m IR0
Instruction A ,IR0+
Stores the PLC memory
address of m in IR0.
Repeats the process
in a loop such as
FOR-NEXT.
Example:
Summary of Contents for SYSMAC CP Series
Page 3: ......
Page 32: ...1 Overview 1 4 CP2E CPU Unit Software User s Manual W614 ...
Page 44: ...3 CPU Unit Operation 3 8 CP2E CPU Unit Software User s Manual W614 ...
Page 116: ...6 I O Allocation 6 8 CP2E CPU Unit Software User s Manual W614 ...
Page 144: ...7 PLC Setup 7 28 CP2E CPU Unit Software User s Manual W614 ...
Page 170: ...10 Interrupts 10 14 CP2E CPU Unit Software User s Manual W614 ...
Page 200: ...11 High speed Counters 11 30 CP2E CPU Unit Software User s Manual W614 ...
Page 272: ...12 Pulse Outputs 12 72 CP2E CPU Unit Software User s Manual W614 ...
Page 278: ...13 PWM Outputs 13 6 CP2E CPU Unit Software User s Manual W614 ...
Page 460: ...18 Programming Device Operations 18 28 CP2E CPU Unit Software User s Manual W614 ...
Page 576: ...Revision 2 CP2E CPU Unit Software User s Manual W614 ...
Page 577: ......