NEC uPD72257, Preliminary User'S Manual

Page: 92 / 343

Reset
source
System
reset
PLL reset
SYSCLKCTRL
reset
Purpose
SYSPLLCTRL
reset
PLL
restart
SYSRESET.
SWRESET
yes no no no
reset of all system functions with
continuing clock operation
WDRESET
Synchronization After any reset has been applied the graphics controller is not operable for a
certain time, which depends on the reset source. During this time the Host CPU
must not access the graphics controller, refer to the section "Host CPU
synchronization" below.
4.3.1 PLL restart
A PLL restart requires some attention concerning the timing of the internally
generated SYSRESET signal.
In order to ensure a stable internal main system clock HCLK prior to release of all
internal modules, the internal SYSRESET remains active for some time after the
PLL restart reset is released. As a consequence all modules will not be in operation
until SYSRESET is deasserted.
The diagrams below outline the initial start timing, initiated by an external
RESET, and restart timing, initiated by SYSRESET.PLLRESET = 1.
RESET
RESINT
T
PLLSTART
clear of RESINT
by Host CPU
SYSRESET
Figure 4-4 PLL start timing
PLLRESET
T
PLLSTART
RESINT
clear of RESINT
by Host CPU
SYSRESET
Figure 4-5 PLL restart timing
The start time T
PLLSTART
takes 43000 periods of the oscillator clock CLKIN with
its frequency of the external resonator at XT1/XT2.
Chapter 4 System Controller
92
Preliminary User's Manual S19203EE1V3UM00