5.2.3.3
eeLong command
This command initiates data access in long (28-bit) addressing mode and defines
the access address ADD[27:0].
Byte
2nd byte
1st byte
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Content
ADD[11:4]
ADD[3:0]
L[1:0]
RW
1
Byte
4th byte
3rd byte
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Content
ADD[27:20]
ADD[19:12]
Parameters
•
bit1 = RW: defines the direction of the data transfer:
-
RW = 0: write mode, LBDIN[7:0] from Host CPU (HLBWR active)
-
RW = 1: read mode, LBDIN[7:0] to Host CPU (HLBRD active)
•
bit[3:2] = L[1:0]: defines the data length, i.e. the number of data bytes
to transfer:
-
L[1:0] = 00
B
: 1 data byte (8-bit data)
-
L[1:0] = 01
B
: 2 data bytes (16-bit data)
-
L[1:0] = 10
B
: 4 data bytes (32-bit data)
-
L[1:0] = 11
B
: setting prohibited
•
bit[31:4] = ADD[27:0]: 28-bit address
eeLong byte1
eeLong byte2
eeLong byte3
command
transfer
word
data transfer
L[1:0] = 00
B
L[1:0] = 01
B
L[1:0] = 10
B
eeLong byte4
data byte1
data byte2
data byte3
data byte4
eeLong byte1
eeLong byte2
eeLong byte3
command
transfer
eeLong byte4
halfword
data transfer
data byte1
data byte2
byte
data transfer
data byte
time
time
time
eeLong byte1
eeLong byte2
eeLong byte3
command
transfer
eeLong byte4
Figure 5-5 eeLong command flow
Chapter 5
Host CPU Interface
128
Preliminary User's Manual S19203EE1V3UM00
Summary of Contents for uPD72257
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