NEC uPD72257, Preliminary User'S Manual

Page: 104 / 343

4.7.3.2 SYSCLKCTRL - Clock control register
This register defines the division factors for the main system clock HCLK and
Video Output clocks VO0CLK/VO1CLK.
It further allows to en-/disable the clock of the external SDRAM and, in case of
Ravin-L, the internal SRAM.
The reset value of this register is controlled by the boot mode function, thus
depends on the level of the MODE4, MODE7 and MODE9 pins after release of
RESET.
Access This register can be read/written in 32-bit units.
Address <SysC_Base> + 04
H
Initial Value The initial value of SYSCLKCTRL is specified by some of the external MODE pins,
refer to below description of "Reset values". This register is initialized by the
external RESET.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDR
EN
IRAM
CLK
EN
a
0 0 0 0 0 0 0 0 VO1DIV[5:0]
R/W R/W R R R R R R R R R/W
a
Ravin-L only
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 BUSDIV[1:0] 0 0 VO0DIV[5:0]
R R R R R R R/W R R R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Bit Bit name Function
31 SDREN
SDREN enables/disables the external SDRAM
0 SDRAM disabled
1 SDRAM enabled
The reset value of SDREN takes on the level of MODE7 after reset.
30 IRAMCLKEN
IRAMCLKEN enables/disables the internal SRAM (Ravin-L only)
0 SRAM disabled
1 SRAM enabled
The reset value of IRAMCLKEN takes on the level of MODE9 after reset.
21 to 16 VO1DIV[5:0]
Divider for Video Output clock VO1CLK
0
f
VO1CLK
= f
PLLCLKOUT
/ 2
1
2
f
VO1CLK
= f
PLLCLKOUT
/ 3
... ...
62
f
VO1CLK
= f
PLLCLKOUT
/ 63
63
f
VO1CLK
= f
PLLCLKOUT
/ 64
Chapter 4 System Controller
104
Preliminary User's Manual S19203EE1V3UM00