NEC uPD72257, Preliminary User'S Manual

Page: 172 / 343

6.10.2 Video Input registers details
6.10.2.1 VInCONTROL - Video Input control register
This register holds all control bits to operate the Video Input.
Access This register can be read/written in 32-bit units.
Address <VIn_Base> + 18
H
Initial Value 0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DITHEN[3:0]
RGB
SEL
YUVS
EL
SYNC
INV
SYNCSEL[1:0]
CLK
PH
RGB
EN
CAP
EN
R R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Bit Bit name Function
11 to 8 DITHEN[3:0]
Dither control – enables dithering and sets the number of bits to be used for dithering
0000
B
dithering disabled
0001
B
one bit (0) used for dithering
0010
B
two bits (0 - 1) used for dithering
0100
B
three bits (0 - 2) used for dithering
1000
B
four bits (0 - 3) used for dithering
7 RGBSEL
Selects RGB input format
0 input format is RGB(565)
1 input format is RGB(666)
6 YUVSEL
Selects YUV(4:2:2) input format
0 input format is Y1:U:Y2:V
1 input format is U:Y1:V:Y2
5 SYNCINV
Selects polarity of external synchronization signal
0 no inversion of VInSYNC1/VInSYNC2 (active high)
1 inversion of VInSYNC1/VInSYNC2 (active low)
4 to 3 SYNCSEL[1:0]
Synchronization signal selection
00
B
use ITUR-R656 embedded sync mode
01
B
use VInSYNC1 as CSYNC signal
10
B
use VInSYNC1 as HSYNC and VInSYNC2 as VSYNC signal
11
B
reserved
2 CLKPH Clock phase for data input
Chapter 6 Video Input (Ravin-M only)
172
Preliminary User's Manual S19203EE1V3UM00