NEC uPD72257, Preliminary User'S Manual

Page: 102 / 343

Table 4-5 PLL output clock configuration
NDIV[6:0] n = NDIV + 1 MDIV[6:0] m = MDIV + 1 PDIV[1:0] p = PDIV
f
PLLCLKOUT
[MHz}
0000000
B
to
1011011
B
invalid
0000000
B
invalid
00
B
0 100 - 160
1011100
B
93
0000001
B
2
01
B
1 50 - 100
1011101
B
94
0000010
B
3
10
B
2 25 - 50
1011110
B
95
0000011
B
4
11
B
invalid invalid
1011111
B
96
0000100
B
5
1100000
B
97
0000101
B
6
1100001
B
98 ... ...
1100010
B
99
1111101
B
126
1100011
B
100
1111110
B
127
1100100
B
to
1111111
B
invalid
1111111
B
128
If frequency dithering is enabled (SYSPLLCTRL.PC = 1), following values must be
defined additionally:
Table 4-6 PLL output clock dither parameters configuration
ADJ[2:0]
Frequency
dither range
MDL[1:0]
Modulation
frequency range
S[1:0]
f
VCOIN
= f
CLKIN
/ m
range [MHz]
000
B
ca. 0.5%
00
B
15 KHz to 25 KHz
00
B
1.00 ≤ f
VCOIN
< 1.20
001
B
ca. 1.0 %
01
B
25 KHz to 35 KHz
01
B
1.20 ≤ f
VCOIN
< 1.45
010
B
ca. 2.0 %
10
B
34 KHz to 46 KHz
10
B
1.45 ≤ f
VCOIN
< 1.70
011
B
ca. 3.0 %
11
B
45 KHz to 65 KHz
11
B
1.70 ≤ f
VCOIN
< 2.00
100
B
ca. 4.0 %
101
B
ca. 5.0 %
110
B
to 111
B
invalid
The default (reset) value of SYSPLLCTRL is determined by the MODE[5:4] pin level
at de-assertion of RESET. Thus one out of 4 default reset PLL configurations can
be chosen after reset according to the table below.
Table 4-7 Default PLL modes by MODE[5:4] settings
MODE[5:4] SYSPLLCTRL reset value
Assumed f
CLKIN
Resulting f
PLLCKOUT
00
B
0000 6309
H
(NDIV=99, MDIV=9, PDIV=0, PC=0)
16 MHz 160 MHz
01
B
0000 5F0B
H
(NDIV=95, MDIV=11, PDIV=0, PC=0)
20 MHz 160 MHz
10
B
B510 6309
H
(NDIV=99, MDIV=9, PDIV=0, PC=1,
ADJ=5, MDL=3, S=2)
16 MHz
160 MHz
(dithering on:
modulation frequency 45 - 65 KHz,
dither range ca. 5%)
Chapter 4 System Controller
102
Preliminary User's Manual S19203EE1V3UM00