NEC uPD72257 Preliminary User'S Manual Download Page 64

Page: 64 / 343

Host-I/F LBus

LBus

ADBus

External data bus width 32

External SRAM size 64 MB

64 MB

128 KB

32 MB

64 MB

–

Video Outputs 1

Video Input ITU

ITU

RGB/ITU

ITU

Pin number

Option 7a Option 7b Option 7c Option 7d Option 7e Option 9

DGND33

MA14

VI0R1_ITU1

100

MA13

VI0R0_ITU0

101

VI0CLK

102

VO1G4

103

MCS1

VO1R4

104

MSWR

VO1R3

105

MSOE

VO1R2

106

VO1G3

107

VO1G2

108

DVDD15

109

DGND15

110

MSBEN1

VO1R5

111

MSBEN0

unused

112

DGND33

113

DVDD33

114

MA21

VO1G0

115

VO1G1

116

MA23

VO1R1

117

MA22

VO1B1

118

VO1R5

VI0SYNC2

119

VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0G1_ITU7 VI0SYNC1

120

VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0G0_ITU6 VI0B5

121

VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 VI0R5_ITU5 VI0B4

122

VI0R4_ITU4 VI0R4_ITU4 VI0R4_ITU4 VI0R4_ITU4 VI0R4_ITU4 VI0B3

123

VI0R3_ITU3 VI0R3_ITU3 VI0R3_ITU3 VI0R3_ITU3 VI0R3_ITU3 VI0B2

124

VI0R2_ITU2 VI0R2_ITU2 VI0R2_ITU2 VI0R2_ITU2 VI0R2_ITU2 VI0B1

125

VI0R1_ITU1 VI0R1_ITU1 VI0R1_ITU1 VI0R1_ITU1 VI0R1_ITU1 VI0B0

126

VI0R0_ITU0 VI0R0_ITU0 VI0R0_ITU0 VI0R0_ITU0 VI0R0_ITU0 VI0G5

127

MA24

VO0EN

MA24

VO0EN

128

HINT

129

DGND33

130

DGND33

131

DVDD33

132

VO1VSYNC VO1VSYNC VO1VSYNC VO1VSYNC VO1VSYNC VO1VSYNC

133

VO1HSYNC VO1HSYNC VO1HSYNC VO1HSYNC VO1HSYNC VO1HSYNC

Chapter 2

Pin Functions

Preliminary User's Manual S19203EE1V3UM00

Summary of Contents for uPD72257

Page 1: ...Preliminary User s Manual PD72256 PD72257 Graphics Controllers Hardware Document No S19203EE1V3UM00 Date published July 07 2009 NEC Electronics 2008 Printed in Germany...

Page 2: ...cuits software and information While NEC Electronics endeavors to enhance the quality reliability and safety of NEC Electronics products customers agree and acknowledge that the possibility of defects...

Page 3: ...nics they must contact an NEC Electronics sales representative in advance to determine NEC Electronics willingness to support a given application Note 1 NEC Electronics as used in this statement means...

Page 4: ...ngdom Branch Cygnus House Sunrise Parkway Linford Wood Milton Keynes MK14 6NP U K Tel 01908 691133 Succursale Fran aise 9 rue Paul Dautier B P 52 78142 Velizy Villacoublay C dex France Tel 01 30675800...

Page 5: ...ess High order at high stage and low order at low stage Note Additional remark or tip Caution Item deserving extra attention Numeric notation Binary xxxx or xxxB or xxxB Decimal xxxx Hexadecimal xxxxH...

Page 6: ...ge field denotes the half frame holding the even respectively odd lines of a frame in interlaced video mode thus one entire frame is made up of two fields Trademarks AHB stands for AMBA Advanced High...

Page 7: ...4 System Controller 86 4 1 Functional Overview 87 4 2 Clock Generator 88 4 2 1 PLL configuration 89 4 2 2 Main system clock 90 4 2 3 Video Output clocks 90 4 2 4 Internal RAM clock Ravin L only 90 4 3...

Page 8: ...on status information 156 6 3 Video Capturing 156 6 3 1 Video capturing modes 156 6 3 2 Start and stop of video capturing 157 6 4 Scaling Cropping and Storing 158 6 4 1 Cropping 159 6 4 2 Scaling 160...

Page 9: ...Formats 223 8 4 1 Source and destination data 223 8 4 2 Texture colour formats 223 8 4 3 Framebuffer colour formats 223 8 5 Rendering Pipeline 225 8 5 1 Coordinate transformation 225 8 5 2 Rasterizat...

Page 10: ...2 SDRAM Refresh Control 297 9 3 Static Memory Interface 302 9 3 1 Static RAM timing 302 9 4 Address Decoder 307 9 4 1 Chip select configuration 307 9 4 2 Address adjustment 311 9 5 Memory Controller P...

Page 11: ...n behind Note Throughout this document the name Ravin L is used for the PD72256 and Ravin M for the PD72257 device The graphics controllers provide following features Table 1 1 Ravin L and Ravin M fea...

Page 12: ...Output 0 VO0HSYNC VO0VSYNC VO0CLK VO0EN VO0R 5 0 VO0G 5 0 VO0B 5 0 System Controller XT1 XT2 RESET Host I F HLBD 7 0 HADD 15 0 LBus I F ADBus I F HADBEN 1 0 HADA 20 0 HLBWR HLBRD HLBCS HLBDRQ HINT HAD...

Page 13: ...sed to give the external Host CPU access the control registers of the System Controller Video Input and Drawing Engine The Host I F module is the only APB master AHB The main purpose of the AHB is to...

Page 14: ...ck HCLK that is supplied to most modules It is also used to set up and generate the pixel clocks VO0CLK and VO1CLK for the Video Output modules Another important task of the System Controller is the g...

Page 15: ...NMUX BUFPUEN 7 0 is also determined by MODE 3 0 Ravin L Ravin L does not feature different pinout options For Ravin L the boot mode pins MODE 3 0 have to be set to 0011B at release of RESET which sets...

Page 16: ...C O 12 VO0VSYNC O 13 VO0CLK O 14 n c I O 5 15 n c I O 5 16 DVDD33 PWR n a 17 DGND33 PWR n a 18 n c I O 5 19 n c I O 5 20 n c I O 5 21 n c I O 5 22 n c I O 5 23 DVDD15 PWR n a 24 DGND15 PWR n a 25 n c...

Page 17: ...3 MD14 I O 4 54 MD13 I O 4 55 MD12 I O 4 56 MD11 I O 4 57 MD10 I O 4 58 DGND15 PWR n a 59 DVDD15 PWR n a 60 MD9 I O 4 61 MD8 I O 4 62 MDDQM1 O 63 DVDD33 PWR n a 64 DGND33 PWR n a 65 MDCLK O 66 MDFBCLK...

Page 18: ...6 n c I 6 97 DVDD33 PWR n a 98 DGND33 PWR n a 99 n c I 6 100 n c I 6 101 DVDD33 I 7 102 n c O 1 103 MCS1 O 104 MSWR O 105 MSOE O 106 n c O 107 n c O 108 DVDD15 PWR n a 109 DGND15 PWR n a 110 MSBEN1 O...

Page 19: ...MA18 O 2 141 MA17 O 2 142 DGND33 PWR n a 143 DVDD33 PWR n a 144 HLBD7 I O 1 145 HLBD6 I O 1 146 HLBD5 I O 1 147 HLBD4 I O 1 148 HLBD3 I O 1 149 HLBD2 I O 1 150 HLBD1 I O 1 151 HLBD0 I O 1 152 HLBRD I...

Page 20: ...ODE4 I O 170 DVDD33 PWR n a 171 DGND33 PWR n a 172 VO0R5_MODE5 I O 173 VO0G0_MODE6 I O 174 VO0G1_MODE7 I O 175 VO0G2_MODE8 I O 176 VO0G3_MODE9 I O n c do not connect this pin leave it open PWR power s...

Page 21: ...5 15 MD22_VO1G1_MA14 I O 5 16 DVDD33 PWR n a 17 DGND33 PWR n a 18 MD21_VO1G0_MA13 I O 5 19 MD20_VO1B5_MCS1 I O 5 20 MD19_VO1B4_MSWR I O 5 21 MD18_VO1B3_MSOE I O 5 22 MD17_VO1B2_MSBEN1 I O 5 23 DVDD15...

Page 22: ...55 MD12 I O 4 56 MD11 I O 4 57 MD10 I O 4 58 DGND15 PWR n a 59 DVDD15 PWR n a 60 MD9 I O 4 61 MD8 I O 4 62 MDDQM1 O 63 DVDD33 PWR n a 64 DGND33 PWR n a 65 MDCLK O 66 MDFBCLK I 7 67 MDCKE O 68 MA11 O...

Page 23: ...I0R1ITU1_MA14 I O 6 100 VI0R0ITU0_MA13 I O 6 101 VI0CLK I 7 102 HADA20_VO1G4 O 1 103 HADA19_VO1R4_MCS1 O 104 HADA18_VO1R3_MSWR O 105 HADA17_VO1R2_MSOE O 106 HADA16_VO1G3_MSBEN3 O 107 HADA15_VO1G2_MSBE...

Page 24: ...0_MA21_VO1B3 I O 2 140 HADD9_MA18_VO1B2 I O 2 141 HADD8_MA17_VO1G5 I O 2 142 DGND33 PWR n a 143 DVDD33 PWR n a 144 HADD7_HLBD7 I O 1 145 HADD6_HLBD6 I O 1 146 HADD5_HLBD5 I O 1 147 HADD4_HLBD4 I O 1 1...

Page 25: ...ODE4 I O 170 DVDD33 PWR n a 171 DGND33 PWR n a 172 VO0R5_MODE5 I O 173 VO0G0_MODE6 I O 174 VO0G1_MODE7 I O 175 VO0G2_MODE8 I O 176 VO0G3_MODE9 I O n c do not connect this pin leave it open PWR power s...

Page 26: ...HADA0_VI0G5_VI0R0ITU0 1 SYSPINMUX BUFPUEN1 102 HADA20_VO1G4 144 HADD7_HLBD7 145 HADD6_HLBD6 146 HADD5_HLBD5 147 HADD4_HLBD4 148 HADD3_HLBD3 149 HADD2_HLBD2 150 HADD1_HLBD1 151 HADD0_HLBD0 2 SYSPINMUX...

Page 27: ...8_VO1VSYNC_MA20 83 MD27_VO1HSYNC_MA19 84 MD26_VO1G5_MA18 87 MD25_VO1G4_MA17 88 MD24_VO1G3_MA16 6 SYSPINMUX BUFPUEN6 91 VI0G1ITU7_MA20_VO1G0 92 VI0G0ITU6_MA19_VO1R1 93 VI0R5ITU5_MA18_VO1R0 94 VI0R4ITU4...

Page 28: ...148 HLBD3 149 HLBD2 150 HLBD1 151 HLBD0 2 BUFPUEN2 127 VO0EN 132 MA15 133 MA14 134 MA13 137 MA19 138 MA20 139 MA21 140 MA18 141 MA17 3 BUFPUEN3 89 n c 90 n c 156 n c 4 BUFPUEN4 42 MD7 43 MD6 44 MD5 45...

Page 29: ...c 20 n c 21 n c 22 n c 25 n c 79 n c 80 n c 81 n c 82 n c 83 n c 84 n c 87 n c 88 n c 6 BUFPUEN6 91 n c 92 n c 93 n c 94 n c 95 n c 96 n c 99 n c 100 n c 7 BUFPUEN7 66 MDFBCLK 101 DVDD33 128 HINT 154...

Page 30: ...up 0 n c If SYSBOOTMODE BOOTMODE9 1 IRAM enabled SYSPINMUX 00FD 0003H PINMUX 3 0 0011B pinout option 3 fixed all SMUXm 0 no SMUX selection fixed BUFPUEN 7 0 FDH internal pull up resistors enabled for...

Page 31: ...GB 6 6 6 16 bit SRAM Flash 16 bit SDRAM Internal RAM VO0EN C H VSYNC Host CPU 8 bit multiplexed bus D 7 0 Figure 2 1 Ravin L pinout 2 3 1 Ravin L pin to signals reference The following table lists the...

Page 32: ...0 DGND33 31 MA0 32 MDA10PC 33 MDBA1 34 MDBA0 35 MCS0 36 MDRAS 37 MDCAS 38 MDWE 39 DVDD33 40 DGND33 41 MDDQM0 42 MD7 43 MD6 44 MD5 45 MD4 46 MD3 47 MD2 48 MD1 49 MD0 50 DVDD33 51 DGND33 52 MD15 53 MD14...

Page 33: ...MA7 72 MA6 73 MA5 74 DGND33 75 DVDD33 76 MA4 77 MA3 78 n c 79 n c 80 n c 81 n c 82 n c 83 n c 84 n c 85 DGND33 86 DVDD33 87 n c 88 n c 89 n c 90 n c 91 n c 92 n c 93 n c 94 n c 95 n c 96 n c 97 DVDD3...

Page 34: ...116 MA23 117 MA22 118 n c 119 n c 120 n c 121 n c 122 n c 123 n c 124 n c 125 n c 126 n c 127 VO0EN 128 HINT 129 DGND33 130 DGND33 131 DVDD33 132 MA15 133 MA14 134 MA13 135 MA12 136 MA10 137 MA19 138...

Page 35: ...BCS 156 n c 157 DVDD15 158 DGND15 159 AVDD15 160 AGND 161 XT1 162 XT2 163 RESET 164 DGND33 165 VO0R0 166 VO0R1 167 VO0R2 168 VO0R3 169 VO0R4 170 DVDD33 171 DGND33 172 VO0R5 173 VO0G0 174 VO0G1 175 VO0...

Page 36: ...PINMUX PINMUX 3 0 in signal groups but single signals of the selected signal groups can be replaced by other SMUX signals via dedicated separate multiplexers The separate multiplexers are controlled b...

Page 37: ...l pinout options are indicated by lower case alphanumeric characters appended to the option numbers 6 and 7 That results in options 6a 6b and 7a to 7e Setting SYSPINMUX SMUXm 1 outputs a dedicated sig...

Page 38: ...LBus 8 bit multiplexed HLBD 7 0 ADBus 16 bit separate HADD 15 0 HADA 20 0 Video Output Video out I F 0 RGB 6 6 6 VO0HSYNC VO0VSYNC VO0EN Video out I F 1 RGB 4 5 4 RGB 5 5 5 RGB 5 6 5 RGB 6 6 6 VO1HSYN...

Page 39: ...Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 39...

Page 40: ...I F 0 18 bit RGB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 32 bit SDRAM I F Mem I F 16bit SD SR Host I F 16bit 2MByte System Control Po...

Page 41: ...it RGB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 16 bit SDRAM SRAM I F Mem I F 16bit SD SR Host I F 16bit 2MByte System Control Power Su...

Page 42: ...6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Input I F ITU656 18 bit RGB 6 6 6 composite VI0SYNC1 or separate VI0SYNC1 VI0SYNC2 32 bit SDRAM SRAM I F Xtal...

Page 43: ...0EN display enable signal Video Output I F 1 16 bit RGB 5 6 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656...

Page 44: ...Chapter 2 Pin Functions 44 Preliminary User s Manual S19203EE1V3UM00...

Page 45: ...GB 6 6 6 composite VO0CSYNC or separate VO0HSYNC VO0VSYNC VO0EN display enable signal Video Output I F 1 18 bit RGB 6 6 6 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1...

Page 46: ...Chapter 2 Pin Functions 46 Preliminary User s Manual S19203EE1V3UM00...

Page 47: ...t RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F Xtal Reset 32 bit SRAM Flas...

Page 48: ...al Video Output I F 1 13 bit RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit SDRAM SRAM I F...

Page 49: ...Pin Functions Chapter 2 Preliminary User s Manual S19203EE1V3UM00 49...

Page 50: ...VO0HSYNC VO0VSYNC VO0EN display enable signal Video Output I F 1 18 bit RGB 6 6 6 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register V...

Page 51: ...ay enable signal Video Output I F 1 13 bit RGB 4 5 4 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 32 bit S...

Page 52: ...Chapter 2 Pin Functions 52 Preliminary User s Manual S19203EE1V3UM00...

Page 53: ...te VO0HSYNC VO0VSYNC Video Output I F 1 15 bit RGB 5 5 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 16 b...

Page 54: ...Chapter 2 Pin Functions 54 Preliminary User s Manual S19203EE1V3UM00...

Page 55: ...1 16 bit RGB 5 6 5 composite VO1CSYNC or separate VO1HSYNC VO1VSYNC or VO1HSYNC and VO1EN via VO1VSYNC selectable by SYSVOCTR register Video Input I F ITU656 18 bit RGB 6 6 6 composite VI0SYNC1 or se...

Page 56: ...VO0B2 VO0B2 8 VO0B3 VO0B3 VO0B3 VO0B3 VO0B3 9 VO0B4 VO0B4 VO0B4 VO0B4 VO0B4 10 VO0B5 VO0B5 VO0B5 VO0B5 VO0B5 11 VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC VO0HSYNC 12 VO0VSYNC VO0VSYNC VO0VSYNC VO0VSYNC VO0V...

Page 57: ...M0 42 MD7 MD7 MD7 MD7 MD7 43 MD6 MD6 MD6 MD6 MD6 44 MD5 MD5 MD5 MD5 MD5 45 MD4 MD4 MD4 MD4 MD4 46 MD3 MD3 MD3 MD3 MD3 47 MD2 MD2 MD2 MD2 MD2 48 MD1 MD1 MD1 MD1 MD1 49 MD0 MD0 MD0 MD0 MD0 50 DVDD33 DVD...

Page 58: ...HSYNC VO1HSYNC 84 MD26 MA18 MD26 VO1G5 VO1G5 85 DGND33 DGND33 DGND33 DGND33 DGND33 86 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 87 MD25 MA17 MD25 VO1G4 VO1G4 88 MD24 MA16 MD24 VO1G3 VO1G3 89 leave open leave...

Page 59: ...DA11 HADA11 MA24 HADA11 HADA11 116 HADA10 HADA10 MA23 HADA10 HADA10 117 HADA9 HADA9 MA22 HADA9 HADA9 118 HADA8 HADA8 VI0SYNC2 HADA8 HADA8 119 HADA7 HADA7 VI0SYNC1 HADA7 HADA7 120 HADA6 HADA6 VI0B5 HAD...

Page 60: ...0 HADD0 HADD0 152 HADRD HADRD HLBRD HADRD HADRD 153 HADWR HADWR HLBWR HADWR HADWR 154 HADWAIT HADWAIT HLBDRQ HADWAIT HADWAIT 155 HADCS HADCS HLBCS HADCS HADCS 156 HADBEN0 HADBEN0 VI0G4 HADBEN0 HADBEN0...

Page 61: ...0 VO0B0 4 VO0B1 VO0B1 VO0B1 VO0B1 VO0B1 VO0B1 5 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 6 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 7 VO0B2 VO0B2 VO0B2 VO0B2 VO0B2 VO0B2 8 VO0B3 VO0B3 VO0B3 VO0B3 VO...

Page 62: ...AS MDCAS MDCAS MDCAS 38 MDWE MDWE MDWE MDWE MDWE MDWE 39 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 40 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 41 MDDQM0 MDDQM0 MDDQM0 MDDQM0 MDDQM0 MDDQM0 42 MD7 MD7...

Page 63: ...D33 DGND33 75 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 76 MA4 MA4 MA4 MA4 MA4 MA4 77 MA3 MA3 MA3 MA3 MA3 MA3 78 MDDQM3 MDDQM3 MDDQM3 MDDQM3 VO1R1 MDDQM3 79 MD31 MD31 MD31 MD31 MD31 MD31 80 MD30 MD30...

Page 64: ...DD33 DVDD33 DVDD33 114 MA21 MA21 MA21 MA21 MA21 VO1G0 115 VO1G1 VO1G1 VO1G1 VO1G1 VO1G1 VO1G1 116 MA23 MA23 MA23 MA23 MA23 VO1R1 117 MA22 MA22 MA22 MA22 MA22 VO1B1 118 VO1R5 VO1R5 VO1R5 VO1R5 VO1R5 VI...

Page 65: ...LBD5 147 HLBD4 HLBD4 HLBD4 HLBD4 HLBD4 HLBD4 148 HLBD3 HLBD3 HLBD3 HLBD3 HLBD3 HLBD3 149 HLBD2 HLBD2 HLBD2 HLBD2 HLBD2 HLBD2 150 HLBD1 HLBD1 HLBD1 HLBD1 HLBD1 HLBD1 151 HLBD0 HLBD0 HLBD0 HLBD0 HLBD0 H...

Page 66: ...ion 7a Option 7b Option 7c Option 7d Option 7e Option 9 170 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 171 DGND33 DGND33 DGND33 DGND33 DGND33 DGND33 172 VO0R5 VO0R5 VO0R5 VO0R5 VO0R5 VO0R5 173 VO0G0 VO...

Page 67: ...used as they are clamped to high level internally Caution According to the chosen pinout option pull up resistors are activated in order to prevent malfunction of the graphics controller due to unspec...

Page 68: ...DGND33 n a DGND33 n a DGND33 n a DGND33 n a 31 MA0 open MA0 open MA0 open MA0 open 32 MDA10PC open MDA10PC open MDA10PC open MDA10PC open 33 MDBA1 open MDBA1 open MDBA1 open MDBA1 open 34 MDBA0 open M...

Page 69: ...8 open MA8 open 71 MA7 open MA7 open MA7 open MA7 open 72 MA6 open MA6 open MA6 open MA6 open 73 MA5 open MA5 open MA5 open MA5 open 74 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 75 DVDD33 n a DVDD33...

Page 70: ...ND15 n a 110 HADA14 open HADA14 open MSBEN1 open HADA14 open 111 HADA13 open HADA13 open MSBEN0 open HADA13 open 112 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 113 DVDD33 n a DVDD33 n a DVDD33 n a DV...

Page 71: ...1 open HADD1 open HLBD1 open HADD1 open 151 HADD0 open HADD0 open HLBD0 open HADD0 open 152 HADRD open HADRD open HLBRD open HADRD open 153 HADWR open HADWR open HLBWR open HADWR open 154 HADWAIT iPU...

Page 72: ...VO0B4 open VO0B4 open 10 VO0B5 open VO0B5 open VO0B5 open VO0B5 open 11 VO0HSYNC open VO0HSYNC open VO0HSYNC open VO0HSYNC open 12 VO0VSYNC open VO0VSYNC open VO0EN open VO0VSYNC open 13 VO0CLK open V...

Page 73: ...D1 open MD1 open MD1 open 49 MD0 open MD0 open MD0 open MD0 open 50 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 51 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 52 MD15 open MD15 open MD15 open MD15 ope...

Page 74: ...en 89 VO1R4 open VO1R4 open VO1R4 open VO1R4 open 90 VO1R3 open VO1R3 open VO1R3 open VO1R3 open 91 unused iPU MA20 open MA20 open VO1G0 open 92 unused iPU MA19 open MA19 open VO1R1 open 93 VO1R0 iPU...

Page 75: ...A24 open MA24 open VO0EN open 128 HINT iPU HINT iPU HINT iPU HINT iPU 129 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 130 DGND33 n a DGND33 n a DGND33 n a DGND33 n a 131 DVDD33 n a DVDD33 n a DVDD33 n...

Page 76: ...2 open VO0R2 open 168 VO0R3 open VO0R3 open VO0R3 open VO0R3 open 169 VO0R4 open VO0R4 open VO0R4 open VO0R4 open 170 DVDD33 n a DVDD33 n a DVDD33 n a DVDD33 n a 171 DGND33 n a DGND33 n a DGND33 n a D...

Page 77: ...MD16 open MD16 open unused iPU 26 MDDQM2 open VO1B1 open MDDQM2 open unused open 27 MA2 open MA2 open MA2 open MA2 open 28 MA1 open MA1 open MA1 open MA1 open 29 DVDD33 n a DVDD33 n a DVDD33 n a DVDD...

Page 78: ...n a DGND33 n a 65 MDCLK open MDCLK open MDCLK open MDCLK open 66 MDFBCLK iPU MDFBCLK iPU MDFBCLK iPU MDFBCLK iPU 67 MDCKE open MDCKE open MDCKE open MDCKE open 68 MA11 open MA11 open MA11 open MA11 op...

Page 79: ...VO1R2 open MSOE open 106 VO1G3 open VO1G3 open VO1G3 open unused open 107 VO1G2 open VO1G2 open VO1G2 open unused open 108 DVDD15 n a DVDD15 n a DVDD15 n a DVDD15 n a 109 DGND15 n a DGND15 n a DGND15...

Page 80: ...en HLBD7 open HLBD7 open HLBD7 open 145 HLBD6 open HLBD6 open HLBD6 open HLBD6 open 146 HLBD5 open HLBD5 open HLBD5 open HLBD5 open 147 HLBD4 open HLBD4 open HLBD4 open HLBD4 open 148 HLBD3 open HLBD3...

Page 81: ...ND33 n a DGND33 n a DGND33 n a DGND33 n a 172 VO0R5 open VO0R5 open VO0R5 open VO0R5 open 173 VO0G0 open VO0G0 open VO0G0 open VO0G0 open 174 VO0G1 open VO0G1 open VO0G1 open VO0G1 open 175 VO0G2 open...

Page 82: ...During reset all input pins are not active all other pins are in Hi Z state For a period of four oscillator clocks CLKIN with its frequency of the external resonator at XT1 XT2 after reset release al...

Page 83: ...e internal SRAM is enabled The internal SRAM is enabled by SYSCLKCTRL IRAMCLKEN 1 Table 3 1 Ravin L memory and register map internal SRAM enabled Address range Bus Target 0000 0000H to 0000 002FH Host...

Page 84: ...0H to 0000 3FFFH Memory Controller registers 0000 4000H to 0000 4FFFH Reserved 0000 5000H to 07FF FFFFH External memory bus 0800 0000H to FFFF FFFFH Reserved Table 3 3 Ravin L AHB master priorities Pr...

Page 85: ...sters 0000 1E00H to 0000 1EFFH Video Input module registers 0000 1F00H to 0000 1FFFH Reserved 0000 2000H to 0000 2FFFH AHB Video Output 0 registers 0000 3000H to 0000 3FFFH Memory Controller registers...

Page 86: ...ontroller register addresses are given as address offsets to the base address SysC_Base The SysC_Base address of the System Controller is given in the following table System Controller SysC_Base addre...

Page 87: ...stem Controller functions VISEL 1 0 APB Pin mux XT1 XT2 MODE 11 0 WDRESET SWRESET Reset control Boot mode control Video Input control Pin mux control System watchdog Clock generator Registers PLLRESET...

Page 88: ...IRAMCLK VO0CLK VO1CLK IRAMCKEN IRAM clock control Figure 4 2 Clock Generator The entire clock generator is controlled by means of the SYSPLLCTRL and SYSCLKCTRL registers Boot mode The default values...

Page 89: ...cerning the allowed settings of the PLL parameters refer to the description of the SYSPLLCTRL register SYSPLLCTRL MDIV 6 0 SYSPLLCTRL NDIV 6 0 SYSPLLCTRL PC SYSPLLCTRL MDL 1 0 SYSPLLCTRL ADJ 2 0 SYSPL...

Page 90: ...t interfaces The frequencies of VOxCLK is calculated as follows for SYSCLKCTRL VOxDIV 5 0 0 fVOxCLK fPLLCKOUT VOxDIV 5 0 1 for SYSCLKCTRL VOxDIV 5 0 0 fVOxCLK fPLLCKOUT 2 Boot mode The default values...

Page 91: ...n the reset source external RESET An external RESET sets the SYSPLLCTRL register to its default values defined by MODE 5 4 and restarts the PLL with the default parameters in SYSPLLCTRL by user SYSRES...

Page 92: ...to ensure a stable internal main system clock HCLK prior to release of all internal modules the internal SYSRESET remains active for some time after the PLL restart reset is released As a consequence...

Page 93: ...t the end of TPLLSTART the reset interrupt RESINT is asserted which has to be cleared by the Host CPU 4 3 3 Host CPU synchronization Since the graphics controller is not operable until release of the...

Page 94: ...unctions The System Controller incorporates facilities to control several functions of other modules 4 5 1 Internal RAM control Ravin L only Prior using the Ravin L internal RAM its clock IRAMCLK has...

Page 95: ...s particular attention as a special sequence must be applied Refer to the section Start and stop of video capturing 4 5 3 2 Video Input source selection For testing and evaluation purposes the graphic...

Page 96: ...L RGBEN 1 VInCONTROL RGBSEL 0 VOnLCDCONTROL LCDBPP 2 0 110B RGB 666 VInCONTROL RGBEN 1 VInCONTROL RGBSEL 1 VOnLCDCONTROL LCDBPP 2 0 101B VInCONTROL RGBEN 1 VInCONTROL RGBSEL 1 VInSCALING MX 6 0 00H VI...

Page 97: ...on of Video Output synchronization signals can be selected SYSVOCTRL CSYNCSELn 0 separate sync signals VOnVSYNC VOnHSYNC SYSVOCTRL CSYNCSELn 1 composite sync signal VOnCSYNC output instead of VOnHSYNC...

Page 98: ...set to L level MODE7 enable H disable L SDRAM enable H disable L SDRAM MODE8 set to L level set to H level MODE9 enable H disable L IRAM set to L level MODE10 software application use software applic...

Page 99: ...8 1 Ravin M Refer also to the description of the SYSBOOTMODE register MODE9 Internal RAM enable Ravin L only MODE9 is used to enable the clock for the internal RAM after RESET release MODE9 is stored...

Page 100: ...s of the registers are defined in the first section of this chapter under the key word Register base addresses 4 7 2 System Controller registers write protection Generally all System Controller regist...

Page 101: ...5 24 23 22 21 20 19 18 17 16 S 1 0 MDL 1 0 0 ADJ 1 0 0 0 0 PC 0 0 PDIV 1 0 R W R W R R W R R R R W R R R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 NDIV 6 0 0 MDIV 6 0 R R W R R W Writing to the read o...

Page 102: ...00B 15 KHz to 25 KHz 00B 1 00 fVCOIN 1 20 001B ca 1 0 01B 25 KHz to 35 KHz 01B 1 20 fVCOIN 1 45 010B ca 2 0 10B 34 KHz to 46 KHz 10B 1 45 fVCOIN 1 70 011B ca 3 0 11B 45 KHz to 65 KHz 11B 1 70 fVCOIN 2...

Page 103: ...d fCLKIN Resulting fPLLCKOUT 11B B510 5F0BH NDIV 95 MDIV 11 PDIV 0 PC 1 ADJ 5 MDL 3 S 2 20 MHz 160 MHz dithering on modulation frequency 45 65 KHz dither range ca 5 System Controller Chapter 4 Prelimi...

Page 104: ...1 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SDR EN IRAM CLK ENa 0 0 0 0 0 0 0 0 VO1DIV 5 0 R W R W R R R R R R R R R W a Ravin L only 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 BUSDIV 1 0 0...

Page 105: ...egister for Ravin L and Ravin M Table 4 8 Ravin L SYSCLKCTRL reset values MODE9 IRAMCLKEN MODE7 SDREN MODE4 dividers Reset value 0 0 0 003F 0317H 0 0 1 003F 032FH 0 1 0 803F 0317H 0 1 1 803F 032FH 1 0...

Page 106: ...and HCLK are calculated as follows fVOxCLK fPLLCLKOUT VOxDIV 1 fHCLK fPLLCLKOUT BUSDIV 1 The tables below summarize the default clock settings for Ravin L respectively Ravin M under the assumption th...

Page 107: ...8 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 SWR ESET 0 0 0 PLLR ESET R R R R R R R...

Page 108: ...Bit Bit name Function 11 BOOTMODE11 Level of MODE11 pin the level of MODE11 must be set to 0 thus BOOTMODE11 0 10 BOOTMODE10 Level of MODE10 pin this pin and bit can be used for application purposes b...

Page 109: ...al Value 0000 0001H This register is never modified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 110: ...3 2 1 0 0 0 0 SMUX 91 SMUX 92 SMUX 93 SMUX 94 SMUX 95 SMUX 12 SMUX 78 SMUX 26 SMU X127 PINMUX 3 0 R R R W R W R W R W R W R W R W R W R W R W R W Writing to the read only bits is ignored reading retur...

Page 111: ...ermined by PINMUX 3 0 1 VO1R1 output 10 SMUX93 Pin 93 multiplexer control 0 output determined by PINMUX 3 0 1 VO1R0 output 9 SMUX94 Pin 94 multiplexer control 0 output determined by PINMUX 3 0 1 VO1B1...

Page 112: ...ther information concerning the pin groups 7 to 0 refer to the chapter Pin Function Ravin M For Ravin M SYSBOOTMODE BOOTMODE8 1 the reset value of SYSPINMUX BUFPUEN 7 0 depend on the chosen pin multip...

Page 113: ...UX reset values SYSBOOTMODE BOOTMODE9 SYSPINMUX BUFPUEN SYSPINMUX reset value 7 6 5 4 3 2 1 0 0 1 1 1 0 1 1 0 1 00ED 0000H 1 1 1 1 1 1 1 0 1 00FD 0000H System Controller Chapter 4 Preliminary User s M...

Page 114: ...to 4 VISEL 1 0 Selects the data source of the Video Input 00B no data to Video Input 01B Video Input data source is external video input interface 10B loopback mode 0 Video Input data source is Video...

Page 115: ...K EN VO0 RAM EN CSYN CSEL 0 R R R R R R R R R W R W R W R W R W R W R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 7 VO1VSSEL Controls function...

Page 116: ...tput 0 0 RAM palette disabled 1 RAM palette enabled 0 CSYNCSEL0 Controls generation of composite VO0CSYNC or separate VO0HSYNC VO0VSYNC synchronization signals of Video Output 0 0 VO0HSYNC VO0VSYNC 1...

Page 117: ...2 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AD WAIT ZEN R R R R R R R R R R R R R R R R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function...

Page 118: ...wed Reading of SYSPROTECT returns an undefined value After any reset the write protection is enabled Access This register can be written in 32 bit units Address SysC_Base 2CH Initial Value none 31 30...

Page 119: ...and the interrupt pin HINT Interrupts Following tables define the assignment of the Ravin M respectively Ravin L interrupts Table 5 2 Ravin M interrupt assignments Interrupt HOSTINTFLAG INTINn Group N...

Page 120: ...T Video Output 1 next base address INTIN25 26 VO1VCPINT Video Output 1 vertical compare INTIN26 27 not used INTIN27 28 not used INTIN28 29 not used INTIN29 30 not used INTIN30 31 not used INTIN31 Tabl...

Page 121: ...INTIN18 19 not used INTIN19 20 not used INTIN20 21 DRWINT Drawing Engine common interrupt INTIN21 22 VO0INT Video Output 0 common interrupt INTIN22 23 not used INTIN23 24 not used INTIN24 25 not used...

Page 122: ...s The addresses provided by the Host CPU are decoded by an address decoder and mapped to 3 different areas Host I F register bus for accessing all Host I F controller internal registers APB single mas...

Page 123: ...24 bit short offset addressing mode is provided in order to unload the LBus Additionally a burst transfer mode with automatic address incrementing functions minimizes the overhead of address transfer...

Page 124: ...ShortOffs The eeShort command defines the lower 12 bit of the entire address and initiates the data transfer Thus the short addressing mode allows fast access to a 4 KB data segment by the 2 byte eeSh...

Page 125: ...fered The commands can have up to six byte length followed by a specified number of data bytes Five different commands are available to set the related data transfer modes Following table gives an ove...

Page 126: ...a eeShort access Byte 2nd byte 1st byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content SHADDOFF 11 4 SHADDOFF 3 0 1 1 0 0 Parameters bit 15 4 SHADDOFF 11 0 upper 12 bit of a short address eeShortOf...

Page 127: ...ve bit 3 2 L 1 0 defines the data length i e the number of data bytes to transfer L 1 0 00B 1 data byte 8 bit data L 1 0 01B 2 data bytes 16 bit data L 1 0 10B 4 data bytes 32 bit data L 1 0 11B setti...

Page 128: ...data length i e the number of data bytes to transfer L 1 0 00B 1 data byte 8 bit data L 1 0 01B 2 data bytes 16 bit data L 1 0 10B 4 data bytes 32 bit data L 1 0 11B setting prohibited bit 31 4 ADD 2...

Page 129: ...5535 Byte 2nd byte 1st byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content ADD 11 4 ADD 3 0 1 1 RW 1 Byte 4th byte 3rd byte Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Content ADD 27 20 ADD 19 12 Byt...

Page 130: ...ng the 6 byte eeBstCfg command by two eeNOP commands Thus the entire command transfer is extended to two words eeNOP byte1 eeNOP byte1 eeBstCfg byte1 eeBstCfg byte2 eeBstCfg byte3 word1 word2 command...

Page 131: ...in order to reset the LBus I F s command data flow mechanism Afterwards the Host CPU can restart to send new commands 3 The Host CPU initiates data read transfers but doesn t perform any further read...

Page 132: ...d HOSTCONTROL DRQEN 1 the DMA byte counter can be cleared and restarted by setting HOSTCONTROL DRQEN 1 again By this the Host CPU can restarted the DMA transfer if the byte transfer sequence was inter...

Page 133: ...enable HADBEN 1 0 write strobe HADWR read strobe HADRD chip select HADCS wait HADWAIT 5 3 2 ADBus I F address offset function The external address bus HADA 20 0 allows to address a range of 2 MB In o...

Page 134: ...8 0 base address Instead the offset 0 is used and the resulting address has iADDR 27 13 0 though HOSTBASE0 BASEADDR 8 0 may define an address 0 Thus define HOSTBASE0 BASEADDR 8 0 0 and do not change...

Page 135: ...e next halfword address HADA 1 0 10B read access the word combining process is disrupted and the write accesses are treated as consecutive separate writes Both half words are separately forwarded to t...

Page 136: ...fore the falling edge of the HADRD HADWR strobe The rising edge of the HADRD HADWR strobe sets HADWAIT again to low level The rising edge of the HADCS sets HADWAIT back to high level and completes the...

Page 137: ...1 2 3 4 Figure 5 9 ADBus principle read write timing 1 HADWAIT falling edge because of HADCS falling edge 2 HADWAIT rising edge after HADRD HADWR falling edge 3 HADWAIT falling edge after HADRD HADWR...

Page 138: ...write timing with wait 1 HADWAIT falling edge because of HADCS falling edge 2 HADWAIT rising edge after HADWR falling edge 3 HADWAIT falling edge after HADWR rising edge 4 delayed HADWAIT rising edge...

Page 139: ...s is specified by the L 1 0 parameters of the eeShort eeLong commands the data size of ADBus I F transfers is specified by the ADBus HADBEN 1 0 byte half word and the word combining function word Depe...

Page 140: ...N AHB_OVERRUN AHB_ERR INT15 INT16 INT17 INT18 INT31 INTEN0 INTEN1 INTEN2 INTEN15 INTEN16 INTEN17 INTEN18 INTEN31 Figure 5 12 Interrupt controller HOSTINTFLAG The interrupts are grouped in 2 categories...

Page 141: ...e HOSTINTFLAG register the HOSTSTATUS register contains two status bits that reflect the status of each interrupt group HOSTSTATUS INTA 1 at least one of the group A interrupts is pending HOSTSTATUS I...

Page 142: ...ost I F is performed and completed before the data is available the AHB master underrun interrupt is activated and the interrupt flag HOSTINTFLAG INTIN0 is set If AHB master underrun INT0 is unmasked...

Page 143: ...s base address 0 register HOSTADBASE0 0000 0020H ADBus base address 1 register HOSTADBASE1 0000 0024H ADBus base address 2 register HOSTADBASE2 0000 0028H ADBus base address 3 register HOSTADBASE3 000...

Page 144: ...n 7 CIFNRDY Host I F not ready 0 Host I F is in operation 1 Host I F and Ravin M in reset state 6 DREQ Status of HLBDRQ pin 0 HLBDRQ is active 1 HLBDRQ is inactive 5 INTA Group A interrupt status 0 no...

Page 145: ...er is read 16 bit or 32 bit units the upper bits 15 to 8 respectively 31 to 8 return undefined values Address 0000 000CH Initial Value 0000 002BH This register is never modified 7 6 5 4 3 2 1 0 MAJORR...

Page 146: ...T AT16 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTST AT15 INTST AT14 INTST AT13 INTST AT12 INTST AT11 INTST AT10 INTST AT9 INTST AT8 INTST AT7 INTST AT6 INTST AT5 INTST A...

Page 147: ...21 20 19 18 17 16 INTEN 31 17 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTEN 15 3 INT EN2 INT EN1 INT EN0 R W R W R W R W Bit Bit name Function 31 to 3 INTEN 31 3 Interrupt n control 0 interrupt n n...

Page 148: ...ized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 INTIN 31 17 R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 INTIN 15 3 INT IN2 INT IN1 INT IN0 R W R W R W R W Writing to the read only bits i...

Page 149: ...register is initialized by any reset 7 6 5 4 3 2 1 0 0 0 0 0 0 0 DRQDIR DRQEN R R R R R R R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 1 DRQ...

Page 150: ...HOSTADBASE3 0031H These registers are initialized by any reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 BASEADDR 8 0 0 0 0 WC R R R R W R R R R W Writing to the read only bits is ignored reading re...

Page 151: ...s offsets to the base address VIn_Base The VIn_Base addresses of the Video Input I F is given in the following table Video Input I F VIn_Base address VI0 0000 1E00H Pin functions The availability of V...

Page 152: ...internal 24 bit RGB 888 to framebuffer 16 bit RGB 565 adjustment of YUV input data brightness colour saturation contrast replacement of U and V component with predefined value up downscaling and crop...

Page 153: ...brightness contrast and colour saturation If monochrome images are captured the colour can be changed by replacing U and V by predefined values RGB 888 conversion All further data video data processin...

Page 154: ...a is input via VInR 5 0 VInG 5 0 VInB 5 0 YUV 4 2 2 VInCONTROL RGBEN 0 ITU R656 coform Video Input data format supported orders are Y0 U Y1 V VInCONTROL YUVSEL 1 U Y0 V Y1 VInCONTROL YUVSEL 0 frame li...

Page 155: ...e wise via the ITU 7 0 signals in synchronization with the clock input VInCLK The edge of VInCLK to be used for sampling the video data ITU 7 0 can be selected VInCONTROL CLKPH 0 ITU 7 0 is sampled wi...

Page 156: ...bits in the Video Input status register VInSTATUS FIELD indicates the current field information VInSTATUS VSYNC indicates the current status of the internal VSYNC signal VInSTATUS HSYNC indicates the...

Page 157: ...oller Note If the Video Input module is disabled by SYSVIEN VIEN 0 all Video Input registers can be accessed but writing to the registers is ignored and reading returns undefined values Start of captu...

Page 158: ...s in progressive scan mode The 512 x 300 pixels area starting at x 90 and y 40 shall be captured and scaled to 600 x 225 pixels to be stored in the framebuffer 0 0 PXCNT VInSTARTY 40 VInSTARTX 90 VInS...

Page 159: ...wing lines of the respective field are captured and passed on for further processing In case of progressive capturing VInSTARTY STARTY2 9 0 defines the first line to capture while VInSTARTY STARTY1 9...

Page 160: ...frame the y scaler is reset and the xin and y coordinates are set to address the first pixel of the first line Depending on the y scaling factor a decision is taken whether the current line produces a...

Page 161: ...yes yes reset y scaler y 0 reset x scaler xin xin 1 xin xin 1 y y 1 y y 1 xin 0 yes new frame y scaler x scaler Figure 6 4 Video Input scaler unit 6 4 2 1 Y scaler The y scaler allows downscaling of a...

Page 162: ...n is handed over to the x scaler Note Pin xin and Pyout xin includes the three colour channels R G B frame end no yes yes y y 1 xin 0 yadd y_scale frame end no yes y y 1 new frame line end no no line...

Page 163: ...lour channels C i e is R or G or B xadd xsum 1 xremainder 1 xsum xadd xadd xremainder Cxout xout Cxout xout Cyout xin xremainder Cxout xout Cxout xout Cyout xin xadd xsum xsum xadd Cxout xout 0 xsum 0...

Page 164: ...2 pixels VInSTRIDEX 0000 0260H is the correct setting 8 pixels 16 bytes are left unused The start address of the first captured pixel is set to VInSTARTADDR2 0010 0000H The entire captured field occup...

Page 165: ...ble in the original YUV 4 2 2 signal from the ITU R656 source The U and V values are assigned to both of the YUV 4 2 2 two macro pixels YUV422 Y0U Y1V YUV444 Y0UV Y1UV The converter allows to convert...

Page 166: ...um 235 and minimum 16 value Amplification mode In amplification mode VInADJUSTLEVEL ADJMODE 0 the colour saturation can be changed by amplifying the U and V values The amplification factors are set by...

Page 167: ...or red and blue The data manipulation of the dithering unit can be represented as follows R5 4 0 R8 7 0 RNG k 0 and 0xF8 3 G6 5 0 G8 7 0 RNG k 1 0 and 0xFC 2 B5 4 0 B8 7 0 RNG k 0 and 0xF8 3 6 8 Video...

Page 168: ...r one or two framebuffers in the memory The framebuffer address the FIFO content is written to is defined by registers VInSTARTADDR1 base address of first field framebuffer denotes the address of the...

Page 169: ...an undefined address range via the first field framebuffer start address register VInSTARTADDR1 second field framebuffer start address register VInSTARTADDR2 the bus error interrupt VInAHEINT is gene...

Page 170: ...CTSL 11 0 active unscaled scanline number The scanline interrupt VOnSCLINT is activated under following conditions First field scanline interrupt if VInACTSCANLINE ACTSL 11 0 VInSCANLINEINT SLINT 11 0...

Page 171: ...HEIGHT VIn_Base 14H Video Input control settings VInCONTROL VIn_Base 18H Scaling factors register VInSCALING VIn_Base 1CH Video Input status register VInSTATUS VIn_Base 20H Active scanline register VI...

Page 172: ...number of bits to be used for dithering 0000B dithering disabled 0001B one bit 0 used for dithering 0010B two bits 0 1 used for dithering 0100B three bits 0 2 used for dithering 1000B four bits 0 3 u...

Page 173: ...lock edge of VInCLK 1 RGBEN Selects Video Input data format 0 YUV format 1 RGB format 0 CAPEN Enable Video Input data capture 0 video capture disabled 1 video capture enabled starting with a new frame...

Page 174: ...32 bit units Address VIn_Base 00H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 START1 28 16 R R R R W 15 14 13 12 11 10 9 8...

Page 175: ...bit units Address VIn_Base 04H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 START2 28 16 R R R R W 15 14 13 12 11 10 9 8 7...

Page 176: ...nitial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 MY 5 0 0 0 0 0 0 0 0 0 0 R R W R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1...

Page 177: ...31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 SCWIDTH 10 2 SCWIDTH 1 0 R R R R R R W...

Page 178: ...gister is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SCH...

Page 179: ...n and odd numbers Access This register can be read written in 32 bit units Address VIn_Base 08H Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 180: ...fines the first line to capture whereas STARTY1 9 0 is disregarded Access This register can be read written in 32 bit units Address VIn_Base 0CH Initial Value 0000 0000H This register is initialized b...

Page 181: ...e 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 182: ...24 23 22 21 20 19 18 17 16 AVREP 7 0 AUREP 7 0 R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADJ MOD E 0 0 AY 4 0 OY 7 0 R W R R R W R W Writing to the read only bits is ignored reading returns undefi...

Page 183: ...any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 34SCN 9 6 34SCN 5 0 R R R R R R R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 14SCN 9 6 14SCN 5 0 R R R R R R R W R W...

Page 184: ...R R Bit Bit name Function 13 to 8 FFUSEDW 5 0 Number of words in FIFO 7 VIIDLE Operation status of Video Input 0 capture operation active 1 idle 6 FIELD Current status of the internal field signal 0...

Page 185: ...R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 AFLD ACTSL 11 0 R R R R R Bit Bit name Function 12 AFLD Current status of the internal field signal 0 first field 1 second field 11 to 0...

Page 186: ...nline interrupt for second field enabled 12 FLD1EN Enable scanline interrupt for first field 0 scanline interrupt for first field disabled 1 scanline interrupt for first field enabled 11 to 0 SLINT 11...

Page 187: ...ue 0000 0100H This register is never modified 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAJO...

Page 188: ...ce of a Video Output I F is identified by the index n n 0 1 for example VO0LCDTIMING0 for the VO0 LCD timing register 0 Register base addresses All VOn register addresses are given as address offsets...

Page 189: ...1R 5 2 VO1G0 VO1G 5 1 VO1B0 VO1B1 VO1B 5 2 VO1VSYNCb VO1HSYNCc VO1CLK b VOnVSYNC can also output VOnEN configurable in the System Controller c VOnHSYNC can also output VOnCSYNC configurable in the Sys...

Page 190: ...colour look up table to external iRGB 1555 internal true colour 16 bpp RGB 565 to external RGB 565 internal true colour 24 bpp RGB 888 to external RGB 666 display geometry width and height programmabl...

Page 191: ...our Formats The Video Output module operates basically with two different colour formats true colour mode RGB colour data with 24 bpp or 16 bpp resolution is read from the framebuffer and output as 18...

Page 192: ...LCDPALETTE 127 0 Two entries can be written into the palette from a single word write access Note The intensity bit written to the CLUT can be constructed as an OR combination of the LSB of all colour...

Page 193: ...R4 R4 R3 R3 VOnR3 R3 R2 R2 VOnR2 R2 R1 R1 VOnR1 R1 R0 R0 VOnR0 R0 undefined I 7 3 Timing Signals 7 3 1 Display data clock signal The data output clock i e the pixel clock VOnCLK is generated in the Sy...

Page 194: ...also of VOnCSYNC synchronization signals are programmable via the registers VOnLCDTIMING0 and VOnLCDTIMING1 These registers allow also to define the output width and height The unit for the various va...

Page 195: ...deo data valid VOnEN IOE 1 Figure 7 3 VOnHSYNC timing setting VOnVSYNC The diagram below illustrates the line synchronization timing settings The active level of the VOnVSYNC signal can be defined as...

Page 196: ...LCDTIMING2 IHS VOnLCDTIMING2 IVS 1 VOnCSYNC active at low level if VOnLCDTIMING2 IVS VOnLCDTIMING2 IVS IHS thus VOnLCDTIMING2 IHS 0 and VOnLCDTIMING2 IVS 1 or VOnLCDTIMING2 IHS 1 and VOnLCDTIMING2 IVS...

Page 197: ...t base address update interrupt VOnNBAINT is generated Note The VOnLCDUPCURR value may change at any moment and is not normally read It can be read to determine the approximate position within the fra...

Page 198: ...OMP 1 0 11B at start of the front porch You can clear the interrupt by writing VOnLCDICR VCOMPIC 1 VOnNBAINT Next address base update interrupt The LCD next base address update interrupt VOnNBAINT is...

Page 199: ...RIS reflects the occurence of any raw interrupt Any of the bits set here can generate a system interrupt provided it is enabled i e unmasked VOnLCDIMSC Any of the raw interrupts can be enabled unmaske...

Page 200: ...setting VOnLCDTIMING0 6 define the vertical timing parameters by setting VOnLCDTIMING1 7 define the signal polarity of VOnEN VOnHSYNC VOnVSYNC the valid edge of VOnCLK the number of VOnCLK periods per...

Page 201: ...ss register VOnLCDUPBASE VOn_Base 010H Control register VOnLCDCONTROL VOn_Base 018H Interrupt mask set clear register VOnLCDIMSC VOn_Base 01CH Raw interrupt status register VOnLCDRIS VOn_Base 020H Mas...

Page 202: ...zontal back porch width HBP 7 0 specifies the number of VOnCLK periods between deassertion of VOnHSYNC and the start of active data The minimun value of HBP 7 0 is 2 The actual width of the back porch...

Page 203: ...the number of inactive lines at the start of a frame after vertical synchronization period The actual vertical back porch width is VBP 7 0 TVOnHSYNC thus spans the range 0 to 255 lines 23 to 16 VFP 7...

Page 204: ...default value 0 of bit 31 to 27 and 10 to 0 must not be changed Bit Bit name Function 26 bit 26 The default value 0 of this bit must be changed to 1 after reset and must not be altered afterwards 25 t...

Page 205: ...follows VOnCSYNC active at high level if VOnLCDTIMING2 IVS VOnLCDTIMING2 IVS IHS thus VOnLCDTIMING2 IHS VOnLCDTIMING2 IVS 0 or VOnLCDTIMING2 IHS VOnLCDTIMING2 IVS 1 VOnCSYNC active at low level if VO...

Page 206: ...not be altered afterwards 2 The default value 0 of bit 10 to 9 7 to 6 and 4 must not be changed Bit Bit name Function 16 WATERMARK DMA FIFO watermark level WATERMARK defines the number of empty locat...

Page 207: ...565 true colour mode The colour format selection determines the colour format of the pixel data in the framebuffer as well as the format of the display data output 0 LCDEN Video Output control enable...

Page 208: ...his register make sure that the previous address is effectively in use and can be overwritten Therefore wait for the occurence of the VOnNBAINT before rewriting this register Access This register can...

Page 209: ...be read in 32 bit units Address VOn_Base 02CH Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 UPCURRADDR 31 16 R 15 14 13 12 11 10 9...

Page 210: ...IS LNBU IS FUF IS 0 R R R R R R R R R R R R R R R R Bit Bit name Function 4 MBERRORIS AHB master bus error status MBERRORIS is set when the Video Output AHB master interface encounters a bus error res...

Page 211: ...0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR IM VCO MP IM LNBU IM FUF IM 0 R R R R R R R R R R R R W R W R W R W R Bits marked as read only must be written with 0 reading returns undefined values Bit Bit name Fu...

Page 212: ...28 27 26 25 24 23 22 21 20 19 18 17 16 I B 4 0 G 4 0 R 4 0 R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 I B 4 0 G 4 0 R 4 0 R W R W R W R W Bit Bit name Function 31 I Intensity bit a 30 to 26...

Page 213: ...0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR IC VCO MP IC LNBU IC FUF IC 0 W W W W W W W W W W W W W W W W Reading this...

Page 214: ...0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 MBER ROR MIS VCO MP MIS LNBU MIS...

Page 215: ...egisters m 1 to 2 denotes the band limiter number Register base addresses All Drawing Engine register addresses are given as address offsets to the base address DrwE_Base The DrwE_Base address of the...

Page 216: ...Pixel selection FIFO 128 x 107 bit DRWINT APB AHB AHB master interface APB I F Blend unit Framebuffer cache 1024 x 9 bit Texture cache 64 x 32 bit Figure 8 1 Drawing Engine block diagram The Drawing E...

Page 217: ...ribe the whole object If a pixel is inside the object it is selected for rendering if it is outside it is discarded If it is on the edge an alpha value can be chosen proportional to the distance of th...

Page 218: ...Memory read CPU Ravin Figure 8 3 Simplified rendering pipeline setup The Drawing Engine also supports the usage of display lists which makes it possible to decouple CPU and graphics controller effici...

Page 219: ...ng BitBLT features fill copy stretch BitBLT rotate and scale alpha blending bilinear filtering colour conversion subpixel exact placement 8 3 1 3 Vector drawing features The vector Drawing Engine uses...

Page 220: ...and ellipses all conic sections filled or with arbitrary width arcs of 0 360 soft edges alpha gradients render Attribute colour pattern texture Quadratic Bezier approximated by circle arcs arbitrary w...

Page 221: ...In case of the selected colour format is less than 32 bpp then the driver takes care for the correct alignment and copies 32 bit per clock This results in 2 4 times larger copy performance for 8 bpp a...

Page 222: ...e ratios 8 3 3 7 Colour conversion Colour conversion is necessary when using different texture formats than the framebuffer format For saving texture memory several formats are supported with less bpp...

Page 223: ...16 bpp RGB 565 The colour format uses 2 byte per pixel with 5 bit for red 5 bit for blue and 6 bit for green The blue colour is taken as the alpha channel during colour conversion The alpha can be sub...

Page 224: ...ng colour conversion This alpha can be substituted with any alpha during the colourization step in the Drawing Engine 16 bpp aRGB 4444 The colour format uses 2 byte per pixel with 4 bit for every chan...

Page 225: ...pixel is positioned There are six hardware limiters build into the Ravin Drawing Engine In the linear setup a limiter describes a half plane The intersection of all halfplanes is the object If three h...

Page 226: ...to be calculated This is done by the CPU in the driver With this information the Drawing Engine scans the whole bounding box and calculates the decision value for every pixel incrementally A block dia...

Page 227: ...s is a more general form Lets look at a vector form with c n p c y b x a y x f b a n y x p If a point 0 p is on the line then n p c c n p y x f 0 0 0 If you rewrite the constant the equation looks lik...

Page 228: ...n x direction and a step in y direction have to be calculated a p f n e p f n p e p e p f x x x 0 with 0 1 x e a p f n e p f n p e p e p f x x x 0 b p f n e p f n p e p e p f y y y 0 with 1 0 y e This...

Page 229: ...ld mode Then all values above 0 are considered 1 This is used in case antialiasing is not desired e g for shared edges Note In the diagram below following abbreviations are used start DRWLnSTART xadd...

Page 230: ...0 0 The limiter parameters would be x yadd y xadd x y y x start 0 0 In the normalized case normal vector is 2 2 y x x y n The distance between edge and origin is x y y x n p 0 0 0 2 2 y x The limiter...

Page 231: ...y x f y x f y dy bx y x f f d dy cx by by ax f y d cx y b ax y x f In the quadratic case the increments dx dy depend on x and y and are not constant They can be calculated incrementally a c ax c x a x...

Page 232: ...ues above 0 are considered 1 This is used in case antialiasing is not desired Note In the below diagram followign abbreviations are used start1 DRWL1START start2 DRWL2START xadd1 DRWL1XADD xadd2 DRWL2...

Page 233: ...quation 2 2 2 2 2 2 2 r t s ty sx y x y x f With the following assignments the circle equation can be calculated incrementally 2 2 2 2 2 1 1 r t s f t d s c b a This would mean for the limiters with t...

Page 234: ...lter has a single filter parameter w Input value value w yes no value w 1 value output value Figure 8 14 Bandfilter 0 0 2 0 4 0 6 0 8 1 10 5 0 5 10 Input Output after clamp Figure 8 15 Bandfilter outp...

Page 235: ...lamping unit cuts the limiter output to the interval 0 1 Input value value 0 yes no value 0 output value value 1 no value 1 yes Figure 8 16 Clamping unit Drawing Engine Chapter 8 Preliminary User s Ma...

Page 236: ...sents the intersection and the maximum mode the union of the two regions Input value1 Input value2 Value1 value2 yes no output value2 output value1 Figure 8 17 Combiner operated in minmum mode interse...

Page 237: ...e 8 5 8 1 Spanstore Consider the following case If the grey triangle has to be rendered half of the pixel processed by the rendering engine the dotted bounding box would not be drawn This can be optim...

Page 238: ...t empty corner would not be rasterized because of the spanabort optimization 8 5 8 2 Spanabort The second optimization assumes that the object that has to be drawn is convex This means there is only o...

Page 239: ...r optimizations In this case the spanstore delay is used 46 2 28 2 37 85 6 42 2 45 98 3 96 6 79 5 0 10 20 30 40 50 60 70 80 90 100 Triangle A Triangle B Triangle C enumeration coverage Box Box span ab...

Page 240: ...in g A g out b B b A b in b A b Figure 8 24 Colourization step interpolation between the two colour registers A DRWCOLOR1 and B DRWCOLOR2 This general approach can be used to several different colour...

Page 241: ...points in object space x y to 3 points in texture space u v Let there be the following mapping h v u p y x p w v u p y x p v u p y x p 0 0 0 0 2 2 2 2 2 2 1 1 1 1 1 1 0 0 0 0 0 0 While w is the width...

Page 242: ...mapping object space transformation from coordinate system O to O to simplify calculations O u v w h Figure 8 27 Texture mapping texture space texture with width w and height h Chapter 8 Drawing Engin...

Page 243: ...1 dy dx dy dx A then the equation system can be rewritten as 12 11 12 11 0 0 m m A w m m A w This can be easily solved with determinants Let 1 2 2 1 1 det 1 dy dx dy dx A c Then the resulting constant...

Page 244: ...LVXADDI floor dv dx DRWTEXPITCH This is the integer part of dv dx DRWLVYADD floor dv dy DRWTEXPITCH This is the integer part of dv dy DRWLVYXADDF dv dy floor dv dy DRWTEXPITCH dv dx floor dv dx DRWTEX...

Page 245: ...RC_ONE SRC_ALPHA SRC_ONE_MINUS_ALPHA DST_ZERO DST_ONE DST_ALPHA DST_ONE_MINUS_ALPHA The selection of the blend modes is done with the following flags BSF blend source factor is alpha BSI blend source...

Page 246: ..._ZERO DST_ONE_MINUS_ALPHA 0 1 1 1 DST 1 ALPHA SRC_ALPHA DST_ONE 1 0 0 0 SRC ALPHA DST SRC_ALPHA 1 0 0 1 SRC ALPHA SRC_ALPHA DST_ALPHA 1 0 1 0 SRC ALPHA DST ALPHA SRC_ALPHA DST_ONE_MINUS_ALPHA 1 0 1 1...

Page 247: ...d Therefore make sure that DRWSTATUS DLISTACTIVE 0 displaylist reader is idle DRWSTATUS BUSENUM 0 enumeration unit is idle before starting a new register setup Finally write the framebuffer start addr...

Page 248: ...gister 1AH 26 which is DRWCOLOR2 write 00010000H to register 20H 32 which is DRWORIGIN Address word indices Beside referencing a register the indices of an address word can also have other meanings de...

Page 249: ...nce index1 80H index3 index4 Thus always fill all indices after 80H also with the gap index 2 If any of the special indices 80H and FFH are used no register index may follow after them in the same add...

Page 250: ...processing has been stopped because a new display list start has been triggered by writing to the display list start address register DRWDLISTSTART 8 7 2 Interrupt control The three Drawing Engine in...

Page 251: ...WINT mask DRWIRQCTL BUSIRQEM DLISTIRQEM ENUMIRQEM hold clear or DRWSTATUS BUSIRQCLR BUSIRQ DLISTIRQCLR DLISTIRQ ENUMIRQCLR ENUMIRQ Figure 8 30 Interrupt controller Drawing Engine Chapter 8 Preliminary...

Page 252: ...can be chosen from below list Table 8 2 Performance counter trigger events DRWPERFTRIGGER PERFTRIGGERk Event 0 disable performance counter 1 Drawing Engine active cycles 2 framebuffer read access 3 fr...

Page 253: ...25 Secondary colour register DRWCOLOR2 DrwE_Base 68H 26 Pattern register DRWPATTERN DrwE_Base 74H 29 Limiter registers Limiter 1 start value DRWL1START DrwE_Base 10H 4 Limiter 2 start value DRWL2START...

Page 254: ...art DRWLVYADDI DrwE_Base A8H 42 V limiter increment fractional parts DRWLVYXADDF DrwE_Base ACH 43 Colour lookup table for the indexed texture format DRWTEXCLUT DrwE_Base D8H n a b Miscellaneous regist...

Page 255: ...ENABLE LIM6 THRESH OLD LIM5 THRESH OLD LIM4 THRESH OLD LIM3 THRESH OLD LIM2 THRESH OLD LIM1 THRESH OLD QUAD3 ENABLE W W W W W W W W 7 6 5 4 3 2 1 0 QUAD2 ENABLE QUAD1 ENABLE LIM6 ENABLE LIM5 ENABLE LI...

Page 256: ...ld mode 0 disabled 1 enabled 13 LIM5 THRESHOLD Enable limiter 5 threshold mode 0 disabled 1 enabled 12 LIM4 THRESHOLD Enable limiter 4 threshold mode 0 disabled 1 enabled 11 LIM3 THRESHOLD Enable limi...

Page 257: ...imiter 5 0 disabled 1 enabled 3 LIM4ENABLE Enable limiter 4 0 disabled 1 enabled 2 LIM3ENABLE Enable limiter 3 0 disabled 1 enabled 1 LIM2ENABLE Enable limiter 2 0 disabled 1 enabled 0 LIM1ENABLE Enab...

Page 258: ...TEXTURE CLAMPY TEXTURE CLAMPX BC2 BDI BSI BDF BSF 0 W W W W W W W W 7 6 5 4 3 2 1 0 0 0 0 READ FORMAT 3 0 PATTERN SOURCE L5 TEXTURE ENABLE PATTERN ENABLE W W W W W W W W Wrting to bits marked with 0 i...

Page 259: ...ed through BDF 1 invert destination blend factor 1 x 11 BSI src factor will be inverted meaning 1 a or 1 1 depending on BSF 0 use blend factor as specified through BSF 1 invert source blend factor 1 x...

Page 260: ...UMIRQ CLR DLISTIRQ EN ENUMIRQ EN W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit name Function 5 BUSIRQCLR Clear bus error interrupt BUSIRQ 0 no BUSIRQCLR clear 1 clear BUSIRQCLR After...

Page 261: ...ISTIRQ interrupt mask enable 0 disable mask DLISTIRQ 1 enable unmask DLISTIRQ 0 ENUMIRQEN ENUMIRQ interrupt mask enable 0 disable mask ENUMIRQ 1 enable unmask ENUMIRQ Drawing Engine Chapter 8 Prelimin...

Page 262: ...W W W W W W W 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 W W W W W W W W 7 6 5 4 3 2 1 0 0 0 0 0 CFLUSHT X CENABLE TX CFLUSHF B CENABLE FB W W W W W W W W Wrting to bits marked with 0 is ignored Bit Bit na...

Page 263: ...Function 6 BUSIRQ 0 no bus error occurred or interrupt disabled 1 bus error interrupt triggered 5 DLISTIRQ 0 display list not finished or interrupt disabled 1 display list finished interrupt triggere...

Page 264: ...TX CACHE FB CACHE DLR 0 R R R R R R R R 15 14 13 12 11 10 9 8 0 0 0 1 Revisionnumber R R R R R 7 6 5 4 3 2 1 0 Revisionnumber R Bit Bit name Function 20 PERFCOUNT Performance counter 0 no performance...

Page 265: ...er is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COLOR1A 7 0 COLOR1R 7 0 W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COLOR1G 7 0 COLOR1B 7 0 W W Bit Bit name Function 31 to...

Page 266: ...ndex 26 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 COLOR2A 7 0 COLOR2R 7 0 W W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COLOR2G 7 0...

Page 267: ...9 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 12 11 10 9...

Page 268: ...wE_Base 18H DRWL4START DrwE_Base 1CH DRWL5START DrwE_Base 20H DRWL6START DrwE_Base 24H Index DRWL1START 4 DRWL2START 5 DRWL3START 6 DRWL4START 7 DRWL5START 8 DRWL6START 9 Initial Value 0000 0000H This...

Page 269: ...L3XADD DrwE_Base 30H DRWL4XADD DrwE_Base 34H DRWL5XADD DrwE_Base 38H DRWL6XADD DrwE_Base 3CH Index DRWL1XADD 10 DRWL2XADD 11 DRWL3XADD 12 DRWL4XADD 13 DRWL5XADD 14 DRWL6XADD 15 Initial Value 0000 0000...

Page 270: ...L3YADD DrwE_Base 48H DRWL4YADD DrwE_Base 4CH DRWL5YADD DrwE_Base 50H DRWL6YADD DrwE_Base 54H Index DRWL1YADD 16 DRWL2YADD 17 DRWL3YADD 18 DRWL4YADD 19 DRWL5YADD 20 DRWL6YADD 21 Initial Value 0000 0000...

Page 271: ...e 16 16 fixed point inner width of band region Note m 1 to 2 Access This register can be written in 32 bit units Address DRWL1BAND DrwE_Base 58H DRWL2BAND DrwE_Base 5CH Index DRWL1BAND 22 DRWL2BAND 23...

Page 272: ...ss This register can be written in 32 bit units Address DrwE_Base BCH Index 47 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXORI...

Page 273: ...DrwE_Base B4H Index 45 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXPITCH 31 16 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEXPITC...

Page 274: ...its Address DrwE_Base B8H Index 46 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TEXUMASK 20 5 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 275: ...in 32 bit units Address DrwE_Base 90H Index 36 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUSTART 31 16 W 15 14 13 12 11 10 9 8...

Page 276: ...can be written in 32 bit units Address DrwE_Base 94H Index 37 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUXADD 31 16 W 15 14 1...

Page 277: ...can be written in 32 bit units Address DrwE_Base 98H Index 38 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LUYADD 31 16 W 15 14 13...

Page 278: ...written in 32 bit units Address DrwE_Base 9CH Index 39 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVSTARTI 31 16 W 15 14 13 12 1...

Page 279: ...H Index 40 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 W W W W W W W W W W W W W W W W 15 14 13 1...

Page 280: ...can be written in 32 bit units Address DrwE_Base A4H Index 41 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVXADDI 31 16 W 15 14 1...

Page 281: ...can be written in 32 bit units Address DrwE_Base A8H Index 42 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVYADDI 31 16 W 15 14...

Page 282: ...ACH Index 43 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 LVYADDF 15 0 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LVXADDF 15 0 W Bit...

Page 283: ...via display list commands Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CLUTINDEX 7 0 CLUTENTRY 23 16 W W 15 14 13 12 11 10 9 8 7...

Page 284: ...it units Address DrwE_Base 78H Index 30 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SIZEY W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0...

Page 285: ...register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SSD W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PITCH W Bit Bit name Function 31 to 16 SSD Spanstore delay 15 to 0 PIT...

Page 286: ...2 bit units Address DrwE_Base 80H Index 32 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 ORIGIN W 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 287: ...nates Access This register can be written in 32 bit units Address DrwE_Base C8H Index 50 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17...

Page 288: ...RFTRIGGER 2 Selects the internal event that will increment DRWPERFCOUNT2 register 0 disable performance counter 1 Drawing Engine active cycles 2 framebuffer read access 3 framebuffer write access 4 te...

Page 289: ...PERFCOUNT1 DrwE_Base CCH DRWPERFCOUNT2 DrwE_Base D0H Index DRWPERFCOUNT1 51 DRWPERFCOUNT2 52 Initial Value 0000 0000H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 1...

Page 290: ...MemC_Base address of the Memory Controller is given in the following table Memory Controller MemC_Base address MemC 0000 3000H Ravin M pin functions The availability of external memory interface signa...

Page 291: ...abled at system start up Default configuration Upon system start up the external memory interface is configured as follows MCS0 16 MB SDRAM 32 bit data bus width base and alias address 0000 0000H 8 bi...

Page 292: ...les 4 clocks bus idle time 4 clocks Caution As the Ravin L supports only a 16 bit external memory data bus the data bus width has to be changed by setting MEMSCONR DDWIDTH 1 0 00B MEMSCONR SDWIDTH2 1...

Page 293: ...bank select addresses data width 16 bit 32 bit up to 128 MB SDRAM Static memory interface data width 8 bit 16 bit 32 bit up to 128 MB per chips select separate timings parameters and bus widths for ea...

Page 294: ...of the memory bus signals on the off chip PCB the data MD 31 0 signals are sampled with the SDRAM feed back clock MDFBCLK instead of MDCLK for data read accesses Sampling of the read data signals MD...

Page 295: ...sued 3 Auto refresh commands are issued depending on the value MEMSTMG1R INITREF 4 The mode registers of the SDRAM devices are written The Memory Controller performs a power on sequence of the SDRAM u...

Page 296: ...tion The Memory Controller automatically sets the SDRAM devices mode registers during the power up initialization If the SDRAM mode registers shall be rewritten during normal operation set MEMSCTRL SD...

Page 297: ...perations has to be defined by MEMSREFR TREF 15 0 register value MEMSREFR TREF is the value of a free running counter that the refresh logic in the Memory Controller operates on When the count expires...

Page 298: ...lates the minimum frequency in MHz fHCLK MHz num_of_rows 1280 Following table gives some values for the minimum system clock frequency fHCLK for different number of rows to refresh for a maximum burst...

Page 299: ...Ready for new command NOP NOP Auto refresh MEMSTMG0R TRCAR Figure 9 4 SDRAM auto refresh command sequence External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 299...

Page 300: ...P NOP Auto refresh single FSREFA 0 or all FSREFA 1 rows Auto refresh single FSREFB 0 or all FSREFB 1 rows MEMSTMG0R TXSR MEMSTMG0R TRASMIN Figure 9 5 Self refresh command sequence You can force the Me...

Page 301: ...L SREFSTAT 1 before disabling the Memory Controller The self refresh initiation time mainly depends on whether all rows or one row defined by MEMSCTRL FSREFB are to be refreshed before entering self r...

Page 302: ...B static RAM for MCSn MEMSMSKRn MEMTYPE 2 0 010B flash for MCSn If static memory is chosen for a chip select this chip select needs to be associated with one of three timing registers MEMSMTMGRk k 0 t...

Page 303: ...ution Set the read cycle time parameter MEMSMTMGRk TRC 5 0 one clock higher than required by the connected memory TRC HCLK internal MA 24 0 MD 31 0 Address Data MCSn MSOE MSWR MSBEN H Figure 9 6 Stati...

Page 304: ...read cycles TRC TPRC HCLK internal MA 24 2 MA 1 0 Address 00B 01B 10B 11B MD 31 0 D0 D1 D2 D3 MCSn MSOE MSWR MSBEN H Figure 9 7 Flash page read timing In the above diagram following timing parameter...

Page 305: ...old time parameter MEMSMTMGRk TWR defines the number of system clocks the data MD 31 0 and address MA 24 0 is hold stable after deassertion of MSWR TAS TWP TWR HCLK internal MA 24 0 MD 31 0 Address Da...

Page 306: ...turnaround time parameter MEMSMTMGRk TBTA defines the number of system clocks after completion of an access cycle the interface is kept in idle state before starting the next access TBTA TBTA HCLK in...

Page 307: ...HB slave interface Chip select decoder Address adjustment MCSn MA 24 0 MEMCSALIASn MEMSCSLRn MEMSMSKRn MEMSIZE MEMSMCTRL SDATAW MEMSCONR DDATAW Figure 9 10 Address decoder 9 4 1 Chip select configurat...

Page 308: ...er 31 i bits of both match the MCSn is activated The remaining lower address bits i 1 0 are disregarded Below table shows the number of address bits used for comparison in dependency of the chosen mem...

Page 309: ...ernal memory address IMEMADD 31 i Below figure illustrates the generation of the MCSn signal 30 31 31 i 31 i 31 i 0 0 0 0 0 1 1 1 i i 1 mask 30 31 0 i i 1 MEMSCSLRn 30 31 base address match alias addr...

Page 310: ...AM and 0400 0000H to 04FF FFFFH for the flash MEMSCSLR0 0000 0000H MEMSCSLR1 0400 0000H The alias chip select address range shall be 0200 0000H to 03FF FFFFH for the SDRAM and 0500 0000H to 05FF FFFFH...

Page 311: ...Wn 2 0 100B SDRAM setup not supported external address output MA 24 0 internal address maximum memory 225 1 byte 32 MB per chips select external memory with 16 bit data bus static memory setup MEMSMCT...

Page 312: ...CKE low MDCKE high NOP NOP Refresh single row or execute read write access MEMSREFR TREF Figure 9 13 Power down command sequence The Memory Controller can be set into power down mode by setting MEMSCT...

Page 313: ...e request to the SDRAM occurs while the SDRAM is in power down mode the Memory Controller brings the SDRAM out of power down mode and issues the read write access to the SDRAM The Memory Controller th...

Page 314: ...address register 1 MEMSCSLR1 MemC_Base 18H Chip select address mask registers 0 MEMSMSKR0 MemC_Base 54H Chip select address mask registers 1 MEMSMSKR1 MemC_Base 58H Chip select alias address register...

Page 315: ...to 00B Writing to the read only bits is ignored reading returns undefined values Caution 1 Ravin L provides only a 16 bit external memory data bus Thus the default value 01B of bit 14 to 13 DDATAW 1...

Page 316: ...bit 1000B 9 bit 1001B 10 bit 1010B 11 bit default 1011B 12 bit 1100B 13 bit all other prohibited 4 to 3 BKADDRW 1 0 Number of bank address bits 00B 1 bit i e 2 banks 01B 2 bit i e 4 banks default all...

Page 317: ...t be changed Bit Bit name Function 31 to 27 21 to 18 TEXSR 4 0 TXSR 3 0 TEXSR 4 0 and TXSR 3 0 define the time between exit of SDRAM self refresh mode by setting MEMCTRL SREF 0 and the start of the au...

Page 318: ...D 2 0 defines the minimum delay between active and read write commands 000B 1 clock 001B 2 clocks default 111B 8 clocks 5 to 2 TRASMIN 3 0 TRASMIN 3 0 defines the minimum delay between active and prec...

Page 319: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TINIT 15 0 R W Writing to the read only bits is ignored reading returns undefined values Caution The default value 0 of bits 21 and 20 must not be changed Bit Bit nam...

Page 320: ...1H 2 banks open default 10H 1FH 31 banks open 11 SREFSTAT SREFSTAT reflects the status of entering the SDRAM self refresh mode Depending on whether all rows or one row are refreshed defined by MEMSCTR...

Page 321: ...wn mode 1 SREF SREF controls the SDRAM self refresh mode 0 leave SDRAM self refresh mode 1 enter SDRAM self refresh mode 0 INIT By use of INIT the Memory Controller can be forced to initialize the SDR...

Page 322: ...2 bit units Address MemC_Base 10H Initial Value 0000 0410H This register is initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R...

Page 323: ...nitial Value MEMSCSLR0 0000 0000H MEMSCSLR1 0400 0000H These registers are initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSBADDR 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 324: ...R R W R W R W Writing to the read only bits is ignored reading returns undefined values Bit Bit name Function 10 to 8 REGSEL 2 0 REGSEL 2 0 determines which timing parameter register use MEMSMTMGk of...

Page 325: ...00001B 64 KB 00111B 4 MB 00010B 128 KB 01000B 8 MB 00011B 256 KB 01010B 32 MB 00100B 512 KB 01011B 64 MB MCS1 default 00101B 1 MB 01100B 128 MB 00110B 2 MB all other prohibited a No memory connected...

Page 326: ...Initial Value MEMCSALIAS0 0000 0000H MEMCSALIAS1 0400 0000H These registers are initialized by any reset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CSAADDR 31 16 R W 15 14 13 12 11 10 9 8 7 6 5...

Page 327: ...7 6 5 4 3 2 1 0 TWP 5 0 TWR 1 0 TAS 1 0 TRC 5 0 R W R W R W R W a The default value 0 of bit 28 must be changed to 1 after any reset Writing to the read only bits is ignored reading returns undefined...

Page 328: ...clocks of the MSWR active time 00H 1 clock 01H 2 clocks 3H 4 clocks MEMSMTMGR2 default 3FH 64 clocks 9 to 8 TWR 1 0 The write address data hold time parameter TWR 1 0 defines the number of system cloc...

Page 329: ...ion 0CH 13 clocks MEMSMTMGR2 default 3FH 64 clocks Caution Set TRC 5 0 one clock higher than required by the connected memory External Memory Interface Controller Chapter 9 Preliminary User s Manual S...

Page 330: ...bits is ignored reading returns undefined values Caution 1 Ravin L provides only a 16 bit external memory data bus Thus the default value 001B of bit 15 to 13 SDATAW2 2 0 must be changed after any res...

Page 331: ...External Memory Interface Controller Chapter 9 Preliminary User s Manual S19203EE1V3UM00 331...

Page 332: ...0820H Video input enable control SYSVIEN R W 0000 0824H Video output control SYSVOCTRL R W 0000 0828H System watchdog control SYSWDCTRL R W 0000 082CH System control write protection SYSPROTECT W 0000...

Page 333: ...0000 1DA4H V Limiter x axis increment integer part DRWLVXADDI W 0000 1DA8H V Limiter y axis increment integer part DRWLVYADDI W 0000 1DACH V Limiter increment fractional parts DRWLVYXADDF W 0000 1DB4H...

Page 334: ...lette registers VO0LCDPALETTE R W 0000 3000H SDRAM configuration MEMSCONR R W 0000 3004H SDRAM timing 0 MEMSTMG0R R W 0000 3008H SDRAM timing 1 MEMSTMG1R R W 0000 300CH SDRAM control MEMSCTLR R W 0000...

Page 335: ...s VO1LCDRIS R 0000 4024H VO1 Masked interrupt status VO1LCDMIS R 0000 4028H VO1 Interrupt clear VO1LCDICR R 0000 402CH VO1 Current address VO1LCDUPCURR R 0000 4200H 0000 43FCH VO1 Colour palette regis...

Page 336: ...203EE1V1UM00 date published December 02 2008 Chapter Page Description 6 169 generation of VInSCLINT in case of interlaced video changed 6 186 FLD1EN FLD2EN settings corrected 6 186 generation of VInSC...

Page 337: ...Drawing Engine 234 Band filter 234 Base address DrwE_Base 215 Base colour register DRWCOLOR1 265 Blending 245 Bounding box dimension DRWSIZE 284 Cache control register DRWCACHECTL 262 Clamping unit 2...

Page 338: ...255 DRWCONTROL2 258 DRWDLISTIRQ 250 DRWDLISTSTART 287 DrwE_Base 215 DRWENUMIRQ 250 DRWHWREVISION 264 DRWIRQCTL 260 DRWLmBAND 271 DRWLnSTART 268 DRWLnXADD 269 DRWLnYADD 270 DRWLUSTART 275 DRWLUXADD 276...

Page 339: ...Chip select address mask register MEMSMSKRn 324 Chip select alias address registers MEMCSALIASn 326 Chip select base address registers MEMSCSLRn 323 Chip select configuration 307 Control Registers 314...

Page 340: ...de register SYSBOOTMODE 108 Clock control register SYSCLKCTRL 104 Control Registers 100 Pin multiplex control register SYSPINMUX 110 PLL control register SYSPLLCTRL 101 Reset control register SYSRESET...

Page 341: ...enable 97 Colour formats 191 Colour look up table 191 Control Registers 201 Display data output formats 192 FIFO 197 Framebuffer base address 197 Framebuffer base address register VOnLCDUPBASE 208 Ho...

Page 342: ...HSYNC 194 VOnINT 198 VOnLCDCONTROL 206 VOnLCDICR 199 213 VOnLCDIMSC 199 211 VOnLCDMIS 199 214 VOnLCDPALETTE 212 VOnLCDRIS 199 210 VOnLCDTIMING0 202 VOnLCDTIMING1 203 VOnLCDTIMING2 204 VOnLCDUPBASE 208...

Page 343: ......

Search results

Summary of Contents for uPD72257

Reviews:

Related manuals for uPD72257

Brands by name

Popular brands

NEC uPD72257, Preliminary User'S Manual

Search results

Summary of Contents for uPD72257

Reviews:

Related manuals for uPD72257

Brands by name

Popular brands