NEC uPD72257, Preliminary User'S Manual

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• memory size:
-
MEMSMSKRn.MEMSIZE[4:0] = 1 to 17: memory size =
2
MEMSIZE[4:0]-1
• 64 KB
Addressing
The Memory Controller supports a variety of memory sizes between minimum
64 KB up to 4 GB. The size of the memory within the chip select area n has to be
defined by setting MEMSMSKRn.MEMSIZE[4:0].
The memory size is calculated by
memory_size = 2
MEMSIZE[4:0]-1
• 64 K
Thus memory sizes of 64 KB, 128 KB, 256 KB, ..., 64 MB, 128 MB can be chosen.
The address of the chip select area n, i.e. where MCSn is to be activated, is
defined by MEMSCSLRn.CSBADDR[31:16] in the chips select base address
register.
Depending on the chosen memory size MEMSMSKRn.MEMSIZE[4:0], an
appropriate number of upper bits of MEMSCSLRn.CSBADDR[31:i] are compared
with the corresponding bits of the internal memory address IMEMADD[31:i] to be
accessed. If the upper [31:i] bits of both match, the MCSn is activated.
The remaining lower address bits [i-1:0] are disregarded.
Below table shows the number of address bits used for comparison, in
dependency of the chosen memory size.
Table 9-3 Chip select area base addressing
MEMSMSKRn.
MEMSIZE[4:0]
Memory size
Address bits
i
Address bits for
comparison
MEMSCSLRn.CSBADDR
[31:i]
00000
B
none
a
– –
00001
B
64 KB 16 [31:16]
00010
B
128 KB 17 [31:17]
00011
B
256 KB 18 [31:18]
00100
B
512 KB 19 [31:19]
00101
B
1 MB 20 [31:20]
00110
B
2 MB 21 [31:21]
00111
B
4 MB 22 [31:22]
01000
B
8 MB 23 [31:23]
01001
B
16 MB 24 [31:24]
01010
B
32 MB 25 [31:25]
01011
B
64 MB 26 [31:26]
01100
B
128 MB 27 [31:27]
a
No memory connected to chip select n.
Caution
The chip select base address MEMSCSLRn.CSBADDR[31:16] must be aligned
to the memory size, defined by MEMSMSKRn.MEMSIZE[4:0].
Address alias The address aliasing mechanism allows to map two memory areas to the same
chip select area.
Chapter 9 External Memory Interface Controller
308
Preliminary User's Manual S19203EE1V3UM00