NEC uPD72257, Preliminary User'S Manual

Page: 210 / 343

7.7.2.7 VOnLCDRIS - Raw interrupt status register
This register monitors the status of all raw interrupts.
To enable a raw interrupt to generate its corresponding system interrupt it must
be unmasked by setting its mask bit in the VOnLCDIMSC register to 1.
Access
This register can be read in 32-bit units.
Address <VOn_Base> + 020
H
Initial Value
0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0
MBER
ROR
IS
VCO
MP
IS
LNBU
IS
FUF
IS
0
R R R R R R R R R R R R R R R R
Bit Bit name Function
4 MBERRORIS
AHB master bus error status
MBERRORIS is set when the Video Output AHB master interface encounters a bus error
response from the framebuffer.
3 VCOMPIS
Vertical compare
VCOMPIS is set at the beginning of a new frame, i.e. during the vertical synchronization
period. The exact time can be selected by VOnLCDCONTROL.LCDVCOMP[1:0].
2 LNBUIS
LCD next address base update
LNBUIS is set when the current base address register VOnLCDUPCURR has been
successfully updated with the content of the base address register VOnLCDUPBASE.
1 FUFIS
FIFO underflow
FUFIS is set when the DMA FIFO is requested to deliver new output data while it is empty.
Chapter 7 Video Output
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Preliminary User's Manual S19203EE1V3UM00