NEC uPD72257, Preliminary User'S Manual

Page: 13 / 343

HCLK
APB slave
APB AHB
Drawing
Engine
VO0CLK
VO0CLK
HCLK
HCLK
HCLK
HCLK
SYSRESET
SYSRESET
SYSRESET
SYSRESET
SYSRESET
SYSRESET
Video
Output
0
VO0HSYNC
VO0VSYNC
VO0CLK
VO0EN
VO0R[5:0]
VO0G[5:0]
VO0B[5:0]
System
Controller
XT1
XT2
RESET
Host-I/F
HLBD[7:0]
LB
us-I/F
HLBWR
HLBRD
HLBCS
HLBDRQ
HINT
Ex
ter
nal M
emor
y I/F
MD[15:0]
MA[24:0]
MCS0
MCS1
MDCKE
MDCLK
MDBA[1:0]
MDDQM[1:0]
MDFBCLK
MDA10PC
MDRAS
MDWE
MSOE
MSWR
MSBEN[1:0]
MDCAS
C
ommon I/F
SDR
AM-I/F
Sta
tic
memor
y
I/F
APB master
AHB master
AHB master
AHB slave
Slave
AHB slave
AHB slave
AHB master
APB slave
Ravin-L
RAM
160 KB
Figure 1-2 Ravin-L block diagram
Busses The internal modules are linked via two bus systems:
• APB
The APB is used to give the external Host CPU access the control
registers of the System Controller, Video Input and Drawing Engine.
The Host-I/F module is the only APB master.
•
AHB
The main purpose of the AHB is to transfer video and image content
data. Since the Video Input and Output modules, the Drawing Engine
as well as the Host CPU deal with video data, these modules can
access the AHB as bus masters. All video and image data is stored
in framebuffers in external memory and - with Ravin-L - in the internal
RAM. Hence the external and internal memory are connected as
slave AHB clients. The control registers of External Memory I/F
Controller are also accessible via its AHB slave I/F.
The AHB is also used to access the Video Output modules control
registers, whcih are equipped with AHB slave interfaces for that
purpose.
Introduction Chapter 1
Preliminary User's Manual S19203EE1V3UM00
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