7.7.2.3
VOnLCDTIMING2 - Clock and signal polarity control register
This register defines various properties of the control signals:
•
polarity of synchronization and data enable signals
•
valid edge VOnCLK pixel clock
•
number of pixel clocks/line
Access
This register can be read/written in 32-bit units.
Address
<VOn_Base> + 008
H
Initial Value
0000 0000
H
. This register is initialized by any reset.
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
0
0
0
0
0
1
a
CPL
R/W
R/W
R/W
R/W
R/W
R/W
R/W
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
IOE
IPC
IHS
IVS
0
0
0
0
0
0
0
0
0
0
0
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
a
The default value "0" of bit 26 must be changed to "1" after reset.
Bits marked as read-only must be written with "0", reading returns undefined
values.
Caution
1.
Bit 26 of VOnLCDTIMING2 must be set to "1" after reset and must
not be altered afterwards.
2.
The default value "0" of bit 31 to 27 and 10 to 0 must not be changed.
Bit
Bit name
Function
26
bit 26
The default value "0" of this bit must be changed to "1" after reset and must not be altered
afterwards.
25 to 16
CPL[9:0]
Number of VOnCLK clocks per line
CPL[9:0] specifies the number of VOnCLK clocks to the LCD display on each line. This
equals the number of pixels/line, as specified by VoOnLCDTiming0.PPL[5:0].
Thus set CPL[9:0] = 16 • (VOnLCDTiming0.PPL[5:0] + 1)
14
IOE
Video data enable VOnEN active level
0 VOnEN is active high
1 VOnEN is active low
13
IPC
VOnCLK edge selection
0 display data out with rising edge of VOnCLK, i.e. data stable at falling edge
1 display data out with falling edge of VOnCLK, i.e. data stable at rising edge
12
IHS
Horizontal synchronization VOnHSYNC active level
0 VOnHSYNC is active high and inactive low
1 VOnHSYNC is active low and inactive high
11
IVS
Vertical synchronization VOnVSYNC active level
0 VOnVSYNC is active high and inactive low
1 VOnVSYNC is active low and inactive high
Chapter 7
Video Output
204
Preliminary User's Manual S19203EE1V3UM00
Summary of Contents for uPD72257
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