4.2.1 PLL configuration
The PLL is configured by a set of parameters, derived from the SYSPLLCTRL
register.
The frequency of PLLCLKOUT is calculated as follows:
f
PLLCLKOUT
= f
CLKIN
x (n/m) x 1/2
p
The values n, m, p are derived from SYSPLLCTRL register bits:
•
n = SYSPLLCTRL.NDIV[6:0] + 1
•
m = SYSPLLCTRL.MDIV[6:0] + 1
•
p = SYSPLLCTRL.PDIV[1:0]
If frequency dithering is enabled (SYSPLLCTRL.PC = 1), additional parameters
must be set in SYSPLLCTRL:
•
SYSPLLCTRL.S[1:0] must be set in accordance with the frequency
f
VCOIN
= f
CLKIN
/m
•
SYSPLLCTRL.MDL[1:0] determines the modulation frequency
range, i.e. the time the output frequency is from its maximum to its
minimum and vice versa
•
SYSPLLCTRL.ADJ[2:0] determines the frequency dither range, i.e.
the maximum and minimum frequency
Concerning the allowed settings of the PLL parameters refer to the description of
the SYSPLLCTRL register.
SYSPLLCTRL.
MDIV[6:0]
SYSPLLCTRL.
NDIV[6:0]
SYSPLLCTRL.
PC
SYSPLLCTRL.
MDL[1:0]
SYSPLLCTRL.
ADJ[2:0]
SYSPLLCTRL.
S[1:0]
CLKIN
VCOIN
VCOOUT
PLLCLKOUT
PLL & VCO
1/m
1/n
1/2
p
SYSPLLCTRL.
PDIV[1:0]
Figure 4-3 PLL configuration
New PLL parameters set up in SYSPLLCTRL are becoming effective only after a
reset has been applied. While the external RESET takes on one out of the four
predefined parameter sets via the boot mode function, a PLL reset by setting
SYSRESET.PLLRESET = 1 must be applied when SYSPLLCTRL has been
modified by the application software.
For further information concerning the reset function refer to the concerned
chapter
"Resets"
.
Boot mode
The default value of SYSPLLCTRL is subject to the boot mode function and
depends on the MODE[5:4] pin levels at RESET release.
System Controller
Chapter 4
Preliminary User's Manual S19203EE1V3UM00
89
Summary of Contents for uPD72257
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