NEC uPD72257, Preliminary User'S Manual

Page: 108 / 343

4.7.3.4 SYSBOOTMODE - Boot mode register
This register stores the levels of the pins MODE[11:0] upon release of the external
reset RESET.
Access This register can be read in 32-bit units.
Address <SysC_Base> + 0C
H
Initial Value 0000 0MMM
H
with MMM = level of MODE[11:0] pins at reset release
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0
BOOT
MOD
E11
BOOT
MOD
E10
BOOT
MOD
E9
BOOT
MOD
E8
BOOT
MOD
E7
BOOT
MOD
E6
BOOT
MOD
E5
BOOT
MOD
E4
BOOT
MOD
E3
BOOT
MOD
E2
BOOT
MOD
E1
BOOT
MOD
E0
R R R R R R R R R R R R R R R R
Writing to the read-only bits is ignored, reading returns undefined values.
Caution
The default value "0" of bit 13 must not be changed.
Bit Bit name Function
11 BOOTMODE11 Level of MODE11 pin: the level of MODE11 must be set to 0, thus BOOTMODE11 = 0.
10 BOOTMODE10
Level of MODE10 pin: this pin and bit can be used for application purposes by the
application software.
9 BOOTMODE9
Level of MODE9 pin: enable internal SRAM
0 internal SRAM disabled
1 internal SRAM enabled
8 BOOTMODE8
Level of MODE8 pin: selects the graphic controller type
0 Ravin-L
1 Ravin-M
7 BOOTMODE7
Level of MODE7 pin: enable external SDRAM
0 external SDRAM disabled
1 external SDRAM enabled
6 BOOTMODE6 Level of MODE6 pin: the level of MODE6 must be set to 0, thus BOOTMODE6 = 0.
5 to 4
BOOTMODE
[5:4]
Level of MODE[5:4] pins: PLL and clock divider settings
Refer to the description of "SYSPLLCTRL - PLLcontrol register" and "SYSCLKCTRL -
Clock control register".
3 to 0
BOOTMODE
[3:0]
Level of MODE[3:0] pins: pin multiplex settings
Refer to the chapter "Pin Functions".
Chapter 4 System Controller
108
Preliminary User's Manual S19203EE1V3UM00