NEC uPD72257, Preliminary User'S Manual

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9.3.1.3 Static RAM and Flash write timing
The diagram below illustrates the write timing to static RAM or flash memory.
The write address setup time parameter MEMSMTMGRk.TAS defines the number
of system clocks between assertion of MCSn and MSWR.
The write pulse width parameter MEMSMTMGRk.TWP defines the number of
system clocks of the MSWR active time.
The write address/data hold time parameter MEMSMTMGRk.TWR defines the
number of system clocks the data MD[31:0] and address MA[24:0] is hold stable
after deassertion of MSWR.
TAS TWP TWR
HCLK
(internal)
MA[24:0]
MD[31:0]
Address
Data
MCSn
MSOE
MSWR
MSBEN
H
Figure 9-8 Static RAM and flash write timing
In the above diagram following timing parameter settings are used:
• MEMSMTMGRk.TAS = 1: MSWR delayed by 1 clock against MCSn
• MEMSMTMGRk.TWP = 1: 2 clocks MSWR active time
• MEMSMTMGRk.TWR = 1: 1 clock data/address hold time
External Memory Interface Controller Chapter 9
Preliminary User's Manual S19203EE1V3UM00
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