NEC uPD72257, Preliminary User'S Manual

Page: 196 / 343

VSW VBP
VOnVSYNC
IVS = 0
Active lines
VOnVSYNC
IVS = 1
VOnVCPINT
LCDVCOMP[1:0] = 11
B
LCDVCOMP[1:0] = 00
B
LCDVCOMP[1:0] = 01
B
LCDVCOMP[1:0] = 10
B
VFP
LPP
Figure 7-4 VOnVSYNC timing setting
VOnCSYNC If the composite synchronization signal VOnCSYNC is selected to be output via
VOnHSYNC (SYSVOCTRL.CSYNCSELn = 1), the active level of the horizontal and
vertical synchronization signals must be set as follows:
• VOnCSYNC active at high level if
VOnLCDTIMING2.IVS = VOnLCDTIMING2.IVS.IHS, thus
-
VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 0
or
- VOnLCDTIMING2.IHS = VOnLCDTIMING2.IVS = 1
• VOnCSYNC active at low level if
VOnLCDTIMING2.IVS ≠ VOnLCDTIMING2.IVS.IHS, thus
-
VOnLCDTIMING2.IHS = 0 and VOnLCDTIMING2.IVS = 1
or
- VOnLCDTIMING2.IHS = 1 and VOnLCDTIMING2.IVS = 0
7.4 DMA FIFO and Framebuffer Addressing
In order to sustain a high pixel data rate to the display, the pixel data fetched from
the memory is buffered by the DMA FIFO.
The FIFO is 32 words deep by 32 bits wide, thus has a capacity of 32 pixels in
RGB(666), 64 pixels in RGB(565) and 64 pixels in CLUT(8).
If the FIFO fill stage drops below a certain level, the DMA function starts to acquire
new data from the framebuffer for refilling the FIFO.
Chapter 7 Video Output
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Preliminary User's Manual S19203EE1V3UM00