NEC uPD72257, Preliminary User'S Manual

Page: 93 / 343

At the end of T
PLLSTART
the reset interrupt RESINT is asserted, which has to be
cleared by the Host CPU.
4.3.2 Software and Watchdog reset
The user's software reset SWREST is asserted by setting
SYSRESET.SWRESET = 1, while the Watchdog reset WDRESET is triggered by
the System Watchdog.
Both resets effect only a system reset, i.e. the clock generator is not affected and
all clocks continue operation.
SWRESET
WDRESET
T
SWSTART
RESINT
clear of RESINT
by Host CPU
SYSRESET
Figure 4-6 Software and Watchdog reset timing
The time T
SWSTART
is rather short, compared to a PLL restart, and takes 10 periods
of the oscillator clock CLKIN with its frequency of the external resonator at
XT1/XT2.
At the end of T
PLLSTART
the reset interrupt RESINT is asserted, which has to be
cleared by the Host CPU.
4.3.3 Host CPU synchronization
Since the graphics controller is not operable until release of the internal
SYSRESET, the Host CPU must not access the graphics controller until
deassertion of SYSRESET.
Thus the Host CPU has to wait for the end of the T
PLLSTART
respectively
T
SWSTART
period before accessing the graphics controller.
Alternatively the Host CPU can wait until the graphics controller has issued the
reset interrupt RESINT, that marks the end of T
PLLSTART
respectively T
SWSTART
.
The Host CPU has to clear the RESINT by setting the RESINT flag in the
HOSTINTFLAG register to "1", i.e. HOSTINTFLAG.INTIN7 = 1.
Note The reset interrupt RESINT is unmasked, i.e. enabled, after any reset by
HOSTINTENA.INTEN7 = 1.
System Controller Chapter 4
Preliminary User's Manual S19203EE1V3UM00
93