NEC uPD72257, Preliminary User'S Manual

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remainders of the interrupted DMA transfer have to be transferred by a new DMA
process.
5.3 ADBus Interface
The ADBus-I/F delivers high data bandwidth by using the separate 16-bit data
bus HADD[15:0] and 21-bit address bus HADA[20:0].
The address range is extended to 28 bit by offset addressing via four base address
registers, thus giving immediate access to four 512 KB pages.
The data width can be specified to be byte and half-word by use of the byte enable
signals HADBEN[1:0]. The word combining function supports word transfers for
avoiding Host CPU waiting times and minimizing the load of internal busses.
The handshake signal HADWAIT signals towards the Host CPU that the ADBus-
I/F is ready to accept data respectively availability of data. The Host CPU can
evaluate this signal and lengthen the read/write process by inserting wait cycles
upon demand.
5.3.1 ADBus-I/F signals
The Host CPU communicates with the ADBus-I/F via following signals:
• 16-bit data I/O bus HADD[15:0]
• 21-bit address bus HADA[20:0]
• byte enable HADBEN[1:0]
• write strobe HADWR
• read strobe HADRD
• chip select HADCS
• wait HADWAIT
5.3.2 ADBus-I/F address offset function
The external address bus HADA[20:0] allows to address a range of 2 MB. In order
to achieve access to the entire internal 28-bit address range iADDR[27:0] , offset
addressing is used via four (n = 0 to 3) 9-bit base addresses BASEADDRn, defined
in the the HOSTADBASEn registers.
• The base address BASEADDRn[8:0] provides the upper 9 bit of the
internal address, i.e. iADDR[27:19].
• The ADBus-I/F addresses HADA[18:0] contribute the lower 19 bit of
the internal address, i.e. iADDR[18:0], thus they address a 512 KB
page.
• The ADBus-I/F addresses HADA[20:19] select one out of the four
base addresses BASEADDRn[8:0].
Accesses to the internal registers of the Host-I/F and to the registers, connected
to the APB in the 8 KB address range 0000 0000
H
- 0000 1FFF
H
, are not subject
to the HOSTADBASE translation, i.e. the base address 0 is assumed. Thereby the
internal registers are always accessible via the same address range, independent
of any HOSTADBASEn.
Thus the internal 28-bit address internal address iADDR[27:0] is calculated as
follows:
Host CPU Interface Chapter 5
Preliminary User's Manual S19203EE1V3UM00
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