NEC uPD72257, Preliminary User'S Manual

Page: 106 / 343

IRAMCLKEN default
(Ravin-L only)
The IRAMCLKEN default value is subject to the boot mode function and takes on
the level of MODE9 at RESET release:
• MODE9 = 0 IRAMCLKEN = 0: internal SRAM disabled after RESET
• MODE9 = 1 IRAMCLKEN = 1: internal SRAM enabled after RESET
VOxDIV/BUSDIV
default
The VOxDIV[5:0] and BUSDIV[1:0] values are subject to the boot mode function
and take on the level of MODE4 at RESET release.
In conjunction with the default values of the PLL control settings, which depend
on MODE4, two different HCLK, VO0CLK/VO1CLK start-up values can be chosen
for Ravin-L and Ravin-M by setting of the external pins, refer to
Table 4-10
repspectively Table 4-11 .
The frequencies of VOxCLK and HCLK are calculated as follows:
• f
VOxCLK
= f
PLLCLKOUT
/ ( 1)
• f
HCLK
= f
PLLCLKOUT
/ ( 1)
The tables below summarize the default clock settings for Ravin-L respectively
Ravin-M under the assumption that SYSPLLCTRL holds any of the default
settings and has not been modified, i.e. f
PLLCLKOUT
= 160 MHz.
Table 4-10 Ravin-L default clock settings
MODE4
SYSCLKCTRL[23:0]
reset value
Resulting
f
HCLK
Resulting
f
VO0CLK
Resulting
f
VO1CLK
0
3F 0317
H
(BUSDIV=3, VO0DIV=23,
VO1DIV=63)
40 MHz 6.6 MHz 2.5 MHz
1
3F 032F
H
(BUSDIV=3, VO0DIV=47,
VO1DIV=63)
40 MHz 3.3 MHz 2.5 MHz
Table 4-11 Ravin-M default clock settings
MODE4
SYSCLKCTRL[23:0]
reset value
Resulting
f
HCLK
Resulting
f
VO0CLK
Resulting
f
VO1CLK
0
17 0105
H
(BUSDIV=1, VO0DIV=5,
VO1DIV=23)
80 MHz 26.6 MHz 6.6 MHz
1
17 0104
H
(BUSDIV=1, VO0DIV=4,
VO1DIV=23)
80 MHz 32 MHz 6.6 MHz
Chapter 4 System Controller
106
Preliminary User's Manual S19203EE1V3UM00