NEC uPD72257, Preliminary User'S Manual

Page: 193 / 343

Table 7-4 Display data output formats
Signal
True colour modes CLUT mode
RGB(666)
LCDBPP[2:0] = 101
B
RGB(565)
LCDBPP[2:0] = 110
B
iRGB(1555)
LCDBPP[2:0] = 011
B
VOnB5 B5 B4 B4
VOnB4 B4 B3 B3
VOnB3 B3 B2 B2
VOnB2 B2 B1 B1
VOnB1 B1 B0 B0
VOnB0 B0 undefined I
VOnG5 G5 G5 G4
VOnG4 G4 G4 G3
VOnG3 G3 G3 G2
VOnG2 G2 G2 G1
VOnG1 G1 G1 G0
VOnG0 G0 G0 I
VOnR5 R5 R4 R4
VOnR4 R4 R3 R3
VOnR3 R3 R2 R2
VOnR2 R2 R1 R1
VOnR1 R1 R0 R0
VOnR0 R0 undefined I
7.3 Timing Signals
7.3.1 Display data clock signal
The data output clock, i.e. the pixel clock, VOnCLK is generated in the System
Controller's clock generator.
The edge of VOnCLK used by the Video Output to output the pixel data can be
selected:
• VOnLCDTIMING2.IPC = 0: data out with rising VOnCLK edge, data
stable at falling edge
• VOnLCDTIMING2.IPC = 1: data out with falling VOnCLK edge, data
stable at rising edge
Video Output Chapter 7
Preliminary User's Manual S19203EE1V3UM00
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