NEC uPD72257, Preliminary User'S Manual

Page: 119 / 343

Chapter 5 Host CPU Interface
Ravin-M pin
functions
The availability of Host CPU I/F at external pins depend on the selected Ravin-M
pinout option.
Table 5-1 Host CPU I/F Ravin-M pinout options
Bus Signal
Ravin-M pinout option
1, 2, 6 3, 7, 9
ADBus LBus
ADBus
HADA[20:0] √ –
HADD[15:0] √ –
HADBEN[1:0] √ –
HADWR √ –
HADRD √ –
HADWAIT √ –
HADCS √ –
LBus
HLBD[7:0] – √
HLBWR – √
HLBRD – √
HLBDRQ – √
HLBCS – √
Shared HINT √ √
√: available; –: not available
Ravin-L pin functions
The Ravin-L provides only the LBus-I/F pins HLBD[7:0], HLBWR, HLBRD,
HLBDRQ, HLBCS and the interrupt pin HINT.
Interrupts Following tables define the assignment of the Ravin-M respectively Ravin-L
interrupts.
Table 5-2 Ravin-M interrupt assignments
Interrupt
HOSTINTFLAG.INTINn
Group Number Name Cause
A
0 AHB_UNDERRUN AHB overrun INTIN0
1 AHB_OVERRUN AHB underrun INTIN1
2 AHB_ERROR Host-I/F AHB error INTIN2
3 VO0MBEINT Video Output 0 master bus error INTIN3
4 VI0AHEINT Video Input 0 bus error INTIN4
5 VO1MBEINT Video Output 1 master bus error INTIN5
6 not used — INTIN6
7 RESINT Reset generated INTIN7
8 VI0SCLINT Video Input 0 scanline match INTIN8
9 VI0FFOINT Video Input 0 FIFO overflow error INTIN9
10 not used — INTIN10
Preliminary User's Manual S19203EE1V3UM00
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