NEC uPD72257, Preliminary User'S Manual

Page: 206 / 343

7.7.2.4 VOnLCDCONTROL - Control register
This register controls the Video Output operating mode and the pixel parameters.
Access This register can be read/written in 32-bit units.
Address <VOn_Base> + 018
H
Initial Value 0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
WATE
R
MARK
R R R R R R R R R R R R R R R R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0
LCDVCOMP
[1:0]
LCD
PWR
0 0 BGR 0 0 1
a
0 LCDBPP[2:0]
LCD
EN
R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
a
The default value "0" of bit 5 must be changed to "1" after reset.
Bits marked as read-only must be written with "0", reading returns undefined
values.
Caution
1. Bit 5 of VOnLCDCONTROL must be set to "1" after reset and must
not be altered afterwards.
2. The default value "0" of bit 10 to 9, 7 to 6 and 4 must not be changed.
Bit Bit name Function
16 WATERMARK
DMA FIFO watermark level
WATERMARK defines the number of empty locations in the DMA FIFO to initiate new
data read from the framebuffer.
0 ≥ 4 empty locations
1 ≥ 8 empty locations
13 to 12
LCDVCOMP
[1:0]
Vertical compare interrupt control
LCDVCOMP[1:0] defines the time to generate the VOnVCPINT.
00
B
start of vertical synchronization pulse VSYNC
01
B
start of back porch
10
B
start of active video data output
11
B
start of front porch
11 LCDPWR
Display data signals power enable
LCDPRW = 1 enables the display data signals VOnR[5:0], VOnG[5:0], VOnB[5:0].
0 display data signals disabled (output low level)
1 display data signals enabled (active)
Activating of the display data signals requires to enable the Video Output control signals
by LCDEN = 1 prior setting LCDPWR = 1.
Chapter 7 Video Output
206
Preliminary User's Manual S19203EE1V3UM00