NEC uPD72257, Preliminary User'S Manual

Page: 211 / 343

7.7.2.8 VOnLCDIMSC - Interrupt mask register
This register contains the mask bits for all raw interrupts.
The raw interrupt is enabled (unmasked) to generate the respective system
interrupt, when its corresponding mask bit is set to 1.
Access
This register can be read/written in 32-bit units.
Address <VOn_Base> + 01C
H
Initial Value
0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0
MBER
ROR
IM
VCO
MP
IM
LNBU
IM
FUF
IM
0
R R R R R R R R R R R R/W R/W R/W R/W R
Bits marked as read-only must be written with "0", reading returns undefined
values.
Bit Bit name Function
4 MBERRORIM
AHB master error interrupt VOnBEINT enable
0 VOnBEINT disabled (masked)
1 VOnBEINT enabled (unmasked)
3 VCOMPIM
Vertical compare interrupt VOnVCPINT enable
0 VOnVCPINT disabled (masked)
1 VOnVCPINT enabled (unmasked)
2 LNBUIM
LCD next base address update interrupt VOnBAINT enable
0 VOnBAINT disabled (masked)
1 VOnBAINT enabled (unmasked)
1 FUFIM
FIFO underflow interrupt VOnFUFINT enable
0 VOnFUFINT disabled (masked)
1 VOnFUFINT enabled (unmasked)
Video Output Chapter 7
Preliminary User's Manual S19203EE1V3UM00
211