NEC uPD72257, Preliminary User'S Manual

Page: 214 / 343

7.7.2.10 VOnLCDMIS - Masked interrupt status register
This register monitors the status of all system interrupts.
The system interrupts are unmasked (enabled) raw interrupts. The raw interrupts
status is shown in the raw interrupt status register VOnLCDRIS.
The interrupt status can be changed from pending to inactive by writing a 1 to the
corresponding bit in the interrupt clear register VOnLCDICR.
Access
This register can be read in 32-bit units.
Address <VOn_Base> + 024
H
Initial Value
0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0
MBER
ROR
MIS
VCO
MP
MIS
LNBU
MIS
FUF
MIS
0
R R R R R R R R R R R R R R R R
Bit Bit name Function
4 MBERRORMIS
AHB master error interrupt VOnBEINT status bit
0 VOnBEINT pending
1 VOnBEINT inactive
3 VCOMPMIS
Vertical compare interrupt VOnVCPINT status bit
0 VOnVCPINT pending
1 VOnVCPINT inactive
2 LNBUMIS
LCD next address base update interrupt VOnBAINT status bit
0 VOnBAINT pending
1 VOnBAINT inactive
1 FUFMIS
FIFO underflow interrupt VOnFUFINT status bit
0 VOnFUFINT pending
1 VOnFUFINT inactive
Chapter 7 Video Output
214
Preliminary User's Manual S19203EE1V3UM00