NEC uPD72257, Preliminary User'S Manual

Page: 320 / 343

9.6.2.4 MEMSCTLR - SDRAM control register
This register controls various functions of the SDRAM controller.
Access This register can be read/written in 32-bit units.
Address <MemC_Base> + 0C
H
Initial Value 0000 1088
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
OPE
NBK4
R R R R R R R R R R R R R/W R/W R/W
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OPENBK[3:0]
SREF
STAT
0
SDR
MOD
E
0 1 0
FSRE
FA
FSRE
FB
PRC
HALG
PWD
M
SREF INIT
R/W R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Writing to the read-only bits is ignored, reading returns undefined values.
Caution
The default value "010
B
" of bits 8 to 6 must not be changed.
Bit Bit name Function
16 to 12 OPENBK[4:0]
OPENBK[4:0] defines the number of SDRAM internal banks to be open at any time
00
H
1 bank open
01
H
2 banks open (default)
10
H
...
1F
H
31 banks open
11 SREFSTAT
SREFSTAT reflects the status of entering the SDRAM self-refresh mode.
Depending on whether all rows or one row are refreshed - defined by
MEMSCTRL.FSREFB - before entering self-refresh mode, it may take some time before
SDRAM is put into self-refresh mode. SREFSTAT = 1 indicates the completion of this
process.
0 SDRAM not in self-refresh mode
1 SDRAM in self-refresh mode
9 SDRMODE
By SDRMODE the Memory Controller can be forced to do update of SDRAM devices'
mode registers.
0 update completed
1 forces update of SDRAM mode registers
This bit is cleared automatically if the SDRAM mode register update is finished.
5 FSREFA
FSREFA controls the number of refreshes done after SDRAM is taken out of self-refresh
mode
0 refresh one row (default)
1 refresh all rows
4 FSREFB
FSREFB controls number of refreshes done before entering SDRAM self-refresh mode
0 refresh one row (default)
Chapter 9 External Memory Interface Controller
320
Preliminary User's Manual S19203EE1V3UM00