NEC uPD72257, Preliminary User'S Manual

Page: 262 / 343

8.9.2.4 DRWCACHECTL - Cache control register
Internal caches can be enabled /disabled and flushed using this register.
Note that caches will be disabled if a value without its enable bits set is written to
DRWCACHECTL.
Access This register can be written in 32-bit units.
Address <DrwE_Base> + C4
H
Index 49
Initial Value 0000 0000
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
W W W W W W W W
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
W W W W W W W W
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
W W W W W W W W
7 6 5 4 3 2 1 0
0 0 0 0
CFLUSHT
X
CENABLE
TX
CFLUSHF
B
CENABLE
FB
W W W W W W W W
Wrting to bits marked with "0" is ignored.
Bit Bit name Function
3 CFLUSHTX
Flush texture cache
0 do not flush the texture cache
1 flush the texture cache
2 CENABLETX
Texture cache enable
0 disable the texture cache
1 enable the texture cache
1 CFLUSHFB
Flush framebuffer cache
0 do not flush the framebuffer cache
1 flush the framebuffer cache
0 CENABLEFB
Framebuffer cache enable
0 disable the framebuffer cache
1 enable the framebuffer cache
Chapter 8 Drawing Engine
262
Preliminary User's Manual S19203EE1V3UM00