NEC uPD72257, Preliminary User'S Manual

Page: 42 / 343

2.4.2.3 Ravin-M pinout option 3
Setup Ravin-M pinout option 3 is set up by the following register setting:
SYSPINMUX = 00CD 0003
H
PINMUX[3:0] = 0011
B
pinout option 3
all SMUXm = 0 no SMUX selection
BUFPUEN[7:0] = CD
H
internal pull-up resistors enabled for
- group 7: HINT, HADWAIT, HADCS, MDFBCLK,
VI0CLK
- group 6: VI0R[5:0]ITU[5:0], VI0G[1:0]ITU[7:6]
- group 3: VI0G[4:2]
- group 0: VI0G5, VI0B[5:0], VI0SYNC1, VI0SYNC2
Features Ravin-M pinout option 3 provides following features:
• 8-bit LBus Host-I/F
-
multiplexed address/data bus HLBD[7:0]
• Video Output I/F 0
-
18-bit RGB(6/6/6)
- composite VO0CSYNC or separate VO0HSYNC/VO0VSYNC
- VO0EN display enable signal
• Video Input I/F
-
ITU656
- 18-bit RGB(6/6/6)
- composite (VI0SYNC1) or separate (VI0SYNC1/VI0SYNC2)
• 32-bit SDRAM/SRAM -I/F
Xtal, Reset
32-bit SRAM/Flash
Mem I/F 32-bit SDRAM/SRAM
32-bit SDRAM
TF
T
1
8-
bi
t R
G
B(
6/
6/
6)
V
id
eo
O
ut
0
18
-b
it
R
G
B(
6/
6/
6)
H
os
t I
/F
8
bi
t m
ux
ed
3
/5
V
System Control Power Supply
3.3V, 1.5V
Xtal, Reset
TF
T
18
-b
it
R
G
B(
6/
6/
6)
IT
U
65
6,
R
G
B
18
bp
p
System Control Power Supply
3.3V, 1.5V
IT
U
65
6,
R
G
B
18
bp
p
LB
us
H
os
t-I
/F
8
-b
it
m
ultiplexed
V
id
eo
In
IT
U
65
6,
R
G
B(6/6/6)
VO0EN
C/H/VSYNC
H
os
t
C
P
U
D
15
..0
, A
20
..0
H
os
t C
P
U
8
-b
it
m
ultiplexed bus D[7:0]
VI0SYNC1
VI0SYNC2
Figure 2-5 Ravin-M pin layout option 3
Chapter 2 Pin Functions
42
Preliminary User's Manual S19203EE1V3UM00