NEC uPD72257, Preliminary User'S Manual

Page: 330 / 343

9.6.2.10 MEMSMCTRL - Static memory control register
This register defines the size of the data bus of the static memories, associated
with each of the three timing registers MEMSTMGRk.
Access This register can be read/written in 32-bit units.
Address <MemC_Base> + A4
H
Initial Value 0000 2001
H
. This register is initialized by any reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R R R R R R R R R R R R R R R R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDATAW2[2:0]
a SDATAW1[2:0] SDATAW0[2:0] 0 0 0 0 0 0 1
R/W R/W R/W R R R R/W R/W R/W R/W
a
For Ravin-L the default value "001
B
" of SDATAW2[2:0] must be changed to "000
B
".
Writing to the read-only bits is ignored, reading returns undefined values.
Caution
1. Ravin-L provides only a 16-bit external memory data bus. Thus the
default value "001
B
" of bit 15 to 13 (SDATAW2[2:0]) must be
changed after any reset.
2. The default value
-
"0" of bits 3 to 1
- "1" of bit 0
must not be changed.
Bit Bit name Function
15 to 13
12 to 10
9 to 7
SDATAW2[2:0]
SDATAW1[2:0]
SDATAW0[2:0]
SDATAWk[2:0] (k = 0 to 2) defines the width of static memory data bus controlled by
static memory timing register MEMSMTMGRk.
000
B
16 bit
001
B
32 bit for Ravin-M only (MCS1 default)
100
B
8 bit
all other setting prohibited
Caution:
If SDRAM and static memory is connected the width of the static memory data bus,
defined by MEMSMCTRL.SDATAWk[2:0], must not exceed the specified SDRAM
data bus width, defined by MEMSCONR.DDATAW[1:0].
Chapter 9 External Memory Interface Controller
330
Preliminary User's Manual S19203EE1V3UM00