NEC uPD72257, Preliminary User'S Manual

Page: 94 / 343

4.4 System Watchdog
In case the ADBus Host-I/F is used, a continuous assertion of the ADWAIT signal
would block the Host CPU. The System Watchdog detects such situation and
recovers from a possible stalled system.
For this reason the external ADWAIT signal is monitored and in case it is asserted
for more than 325 HCLK clocks the System Watchdog reset WDRESET is
asserted.
WDRESET executes the same reset functions as a software reset by
SYSRESET.SWRESET = 1, in particular it does not stop any clock operations.
The System Watchdog function is disabled per default and must be activated by
SYSWDCRTL.ADWAITZEN = 1.
Caution
Note that ADWAIT is asserted also if just ADCS is asserted and not followed by
any read or write strobe. Such an irregular bus access could also lead to a
WDRESET reset if it lasts too long.
4.5 Modules Control Functions
The System Controller incorporates facilities to control several functions of other
modules.
4.5.1 Internal RAM control (Ravin-L only)
Prior using the Ravin-L internal RAM its clock IRAMCLK has to be enabled. This
is done by
• SYSCLKCTRL.IRAMCLKEN = 0: IRAMCLK disabled
• SYSCLKCTRL.IRAMCLKEN = 1: IRAMCLK enabled
The default setting of SYSCLKCTRL.IRAMCLKEN is subject to the boot mode
function and depends on the level of the MODE9 pin input at release of RESET:
• MODE9 = low level: IRAMCLK disabled per default
• MODE9 = high level: IRAMCLK enabled per default
4.5.2 SDRAM control
Prior using an external SDRAM the SDRAM clock MDCLK has to be enabled. This
is done by
• SYSCLKCTRL.SDREN = 0: MDCLK disabled
• SYSCLKCTRL.SDREN = 1: MDCLK enabled
The default setting of SYSCLKCTRL.SDREN is subject to the boot mode function
and depends on the level of the MODE7 pin input at release of RESET:
• MODE7 = low level: MDCLK disabled per default
• MODE7 = high level: MDCLK enabled per default
Chapter 4 System Controller
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Preliminary User's Manual S19203EE1V3UM00