Channel Earthing
Chassis
+
-
+V
-V
ADC
Non-isolated channel
Non-isolated channel
+
-
+V
-V
ADC
Electrically connected
Figure A.278:
Earthing schematic
Analog to Digital Conversion
Sample rate; per channel
1 S/s to 20 kS/s
ADC resolution; one ADC per channel
24 bit, only 16 bit recorded
ADC type
Sigma Delta (Σ
-
Δ) ADC; Analog Devices AD7764BRUZ
Time base accuracy
Defined by mainframe:
±
3.5 ppm
(1)
; aging after 10 years
±
10 ppm
Binary sample rate
Supported; produces rounded BIN values when calculating FFT's
Maximum binary sample rate
20.48 kS/s
External time base frequency
0 S/s to 20 kS/s
External time base frequency divider
Divide external clock by 1 to 2
20
External time base level
TTL
External time base minimum pulse width
200 ns
(1)
Mainframes using Interface/Controller modules shipped before 2012:
±
30 ppm.
GEN3t
746
I3995-3.1 en HBM: public