6-18
Section 6: 9100 System Operation — SCPI Language
Final Width = 215mm
6.5.3.1
IEEE 488.2 Model
This develops the IEEE 488.1 model into an extended structure with more definite rules.
These rules invoke the use of standard ‘Common’ messages and provide for device-
dependent messages. A feature of the structure is the use of ‘Event’ registers, each with
its own enabling register as shown in Fig. 6.2.
6.5.3.2
9100 Model Structure
The IEEE 488.2 Standard provides for an extensive hierarchical structure with the Status
Byte at the apex, defining its bits 4, 5 and 6 and their use as summaries of a Standard-
defined event structure, which must be included if the device is to claim conformance with
the Standard. The 9100 employs these bits as defined in the Standard.
Bits 0, 1, 2 and 3 and 7 are available to the device designer; only bits 3 and 7 are used in
the 9100, and these are as defined by the SCPI standard.
It must be recognized by the application programmer that whenever the application
program reads the Status Byte, it can only receive summaries of types of events, and
further query messages will be needed to probe the details relating to the events
themselves. For example: a further byte is used to expand on the summary at bit 5 of the
Status Byte.
6.5.3.3
Status Byte Register
In this structure the Status Byte is held in the ‘Status Byte Register’; the bits being
allocated as follows:
Bits: 0 (DIO1), 1 (DIO2) and 2 (DIO3) are not used in the 9100 status byte. They are
always false.
Bit 3 (DIO4)
SCPI-defined Questionable Status Summary Bit (QSS)
Summarizes the state of the ‘Questionable Status data’, held in the ‘Questionable Status
register’ (QSR), whose bits represent SCPI-defined and device-dependent conditions in
the 9100. The QSS bit is true when the data in the QSR contains one or more enabled bits
which are true; or false when all the enabled bits in the byte are false. The QSR and its
data are defined by the SCPI Standard; they are described in Sub-Section 6.5.4.
Bit 4 (DIO5)
IEEE 488.2-defined Message Available Bit (MAV)
The MAV bit helps to synchronize information exchange with the controller. It is true
when a message is placed in the Output Queue; or false when the Output Queue is empty.
The common command
∗
CLS can clear the Output Queue, and the MAV bit 4 of the Status
Byte Register; providing it is sent immediately following a ‘Program Message Terminator’.
6.5.3
9100 Status Reporting - IEEE-488.2 Basics
