Section 6: 9100 System Operation — SCPI Language
6-17
Final Width = 215mm
6.5.2
IEEE-488 and SCPI Standard-Defined Features
(Fig. 6.2)
Two main categories of information are provided: 'Status Summary' information, and 'Event Register' conditions.
6.5.2.1
Status Summary Information and SRQ
The Status Byte consists of four 'summary' bits which notify
events in the 8-bit latched IEEE-488.2-defined ‘Event Status
Register’ (ESB), the two 16-bit latched SCPI-defined registers
(OSS & QSS), and the Output Queue (MAV). Whenever one of
these summary bits is enabled and set true, the Status Byte
summary bit (MSS) is also set true. The buffered bit 'RQS'
follows true when MSS goes true, and will set the IEEE-488
SRQ line true (Note that in Fig 6.2 no arrow points at bit 6 of the
Service Request Enable Register — bit 6 is always enabled).
A subsequent serial poll by the Application Program will
discover that the 9100 was the requesting device (while resetting
RQS false again, MSS remaining true), and which of the
summary bits is true. The
∗
STB? command is an equivalent
command to serial poll, where serial poll is not available.
6.5.2.2
Event Register Conditions
The Status Byte summary bits direct the application program
down the structure towards causal events.
ESB and MAV are standard IEEE-488 features, described in
detail in Sub-Section 6.5.3.
OSS and QSS are features of the SCPI structure, described in
Sub-Section 6.5.4.
6.5.2.3
Access via the Application Program
Referring to Fig. 6.2, take as an example the main Event Status
register:
Enabling the Events
The main Standard-Defined Event Status Register' has a
second 'Event Status Enable Register'. A program command
(
∗
ESE phs Nrf) can be used to set the state of the bits in the
Enable register. This enables or disables the events which
will set the main register's summary bit true.
Reading the Enable Register
A 'query' command (*ESE?) permits the application program
to read the state of the Enable register, and hence find out
which events are enabled to be reported.
Reading the Main Register
Another 'query' command (*ESR?) reads the state of the
main Standard-Defined register, to discover which event
has occurred (i.e. has caused the summary bit to be set true).
Reading this register clears all its bits.
Reporting the Event
If an event is to be reported via the SRQ, its corresponding
enable bit will have been set true, (using the number Nrf).
Each bit in the Standard-Defined register remains in false
condition unless its assigned event occurs, when its condition
changes to true and remains true until cleared by
∗
ESR? or
∗
CLS. This causes the register's summary bit in the Status
Byte also to be set true. If this bit is enabled, then the Status
Byte bit 6 (MSS/RQS) will be set true, and the 9100 will set
the IEEE-488 bus SRQ line true.
SCPI Status Registers
The two SCPI Status registers operate in the same way, using
the appropriate program commands to set the enable registers,
and query commands to discover the condition of the registers.
Subsequent Action
Thus the application programmer can enable any assigned event
to cause an SRQ, or not. The controller can be programmed to
read the Status Byte, using a serial poll to read the Status Byte
register and the true summary bit (ESB, OSS, QSS or MAV).
The application program then investigates the appropriate event
structure until the causal event is discovered. The detail for each
register is expanded in the following paragraphs, and in the
command descriptions.
