AT32WB415
Series Reference Manual
2022.04.13
Page 235
Ver 2.00
ERTC_TSTM
-
-
-
ERTC_TSDT
-
-
-
ERTC_TSSBS
-
-
-
ERTC_SCAL
Y
N
Configurable
when
CALUPDF=0
ERTC_TAMP
N
N
-
ERTC_ALASBS
Y
N
Configurable
when
ALAWF =1
ERTC_ALASBS
Y
N
Configurable
when
ALBWF =1
ERTC_BPRx
N
N
-
Clock and calendar initialization
After the register write protection is unlocked, follow the procedure below for clock and calendar
initialization:
1.
Set the IMEN bit to enter initialization mode
2.
Wait until the initialization flag INITF bit is set
3.
Configure DIVB and DIVA.
4. Configure the clock and calendar values.
5. Leave the initialization mode by clearing the IMEN bit. Wait until the UPDF bit is set, indicating the
completion of the calendar update. The calendar starts counting.
The ERTC also allows the fine-tuning for daylight saving time and clock.
Daylight saving time feature: It is used to increase (ADD1H=1) or decrease (DEC1H=1) one hour in the
calendar, without completing the whole initialization process.
Clock calibration: It is used for the fine calibration of the current clock. If only DECSBS[14: 0] is
configured, the value will be added to the DIVB counter and a clock latency will be generated. If only
ADD1S bit is set, the current clock will increase by one second. If both DECSBS[14: 0] and ADDIS bit
are configured, the clock will increase by a fraction of a second.
Time latency (ADD1S=0): DECSBS/(DIVB+1)
Time advance (ADD1S=1): 1-(DECSBS/(DIVB+1)
Note: To avoid subsecond overflow, SBS[15]=0 must be asserted before setting the ERTC_TADJ register.
Reference clock detection and coarse digital calibration cannot be used at the same time. Thus
when RCDEN=1, coarse digital calibration is not supported.
Reading the calendar
The ERTC offers two different ways to read the calender, that is, synchronous read (DREN=0) and
asynchronous read (DREN=1).
In the case of DREN=0, the clock and calendar values can be obtained by reading a synchronous
shadow register via the PCLK1. The UPDF bit is set each time the shadow register is synchronized with
the ERTC calendar value located in the battery powered domain. The synchronization is performed every
two ERTC_CLK. The shadow register is reset by a system reset. To ensure consistency between the 3
values (ERTC_SBS, ERTC_TIME and ERTC_DATE registers), reading lower-order registers will lock
the values in the higher-order registers until the ERTC_DATE register is read. For example, reading the
ERTC_SBS register will lock the values in the ERTC_TIME and ERTC_DATE registers.
In the case of DREN=1, the ERTC will perform direct read access to the ERTC clock and calendar
located in the battery powered domain with the PCLK1, avoiding the occurrence of errors caused by
time synchronization. In this mode, the UPDF flag is cleared by hardware. To ensure the data is correct
when reading clock and calendar, the software must read the clock and calendar registers twice, and
compare the results of two read operations. If the result is not aligned, read again until that the results
of two read accesses are consistent. Besides, it is also possible to compare the least significant bits of
the two read operations to determine their consistency.
