ARTERY AT32WB415 Series, Reference Manual

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AT32WB415 Series Reference Manual
2022.04.13 Page 307 Ver 2.00
Reset Error Count
Mask ACK
Unmask CHHLTD
Disable Channel
}
else if (CHHLTD)
{
Mask CHHLTD
if (Transfer Done or (Error_count == 3))
{
De-allocate Channel
}
else
{
Re-initialize Channel (in next b_interval - 1 uF/F)
}
}
else if (ACK)
{
Reset Error Count
Mask ACK
}
Before switching to other channles (if any), the application can only write packets based on the number
defined in the MC filed to the transmit FIFO and request queue when the transmit FIFO has free spaces.
The application can determine whether the transmit FIFO has free spaces through the NPTXFEMP bit
in the OTGFS_GINTSTS register.
20.5.3.11 Initialize synchronous IN transfers
Figure 20-9 shows the operation process of a typical synchronous IN transfer. Refer to channel 2 (ch_2).
The assumptions are as follows:
 The application is attempting to receive one largest-packet-size packet (transfer size is 1023
bytes), starting from the next odd frame
 The receive FIFO can store at least one largest-packet-size packet and two status DWORDs per
packet (1031 bytes for full-speed transfer)
 The periodic request queue depth is 4
(1) Common interrupt IN operation process
The sequence of operations shown in Figure 20-9 (channel 2) is as follows:
1.
Initialize channel 2 (according to OTGFS channel initialization requirements). The application must
set the ODDFRM bit in the OTGFS_HCCHAR2 register
2.
Set the CHENA bit in the OTGFS_HCCHAR2 register to write an IN request to the periodic request
queue
3.
The OTGFS host writes an IN request to the periodic request queue each time the CHENA is set in
the OTGFS_HCCHAR2 register
4. The OTGFS host attempts to send an IN token in the next frame (odd)
5. The OTGFS host generates a RXFLVL interrupt as soon as an IN packet is received and written to
the receive FIFO
6. To handle the RXFLVL interrupt, read the received packet status to determine the number of bytes
received, then read the receive FIFO. The application must mask the RXFLVL interrupt before
reading the receive FIFO, and unmask the interrupt after reading the entire packet
7. The controller generates the RXFLVL interrupt when the transfer complete status is written to the
receive FIFO. The application must read and ignore the receive packet when the receive packet is