AT32WB415
Series Reference Manual
2022.04.13
Page 323
Ver 2.00
When an interrupt is generated (XFERC bit in OTGFS_DIEPINTx register), clear the XFERC
interrupt; For the following transaction, repeat step 3-5 until the completion of data transfers.
When an interrupt is generated (INCOMPISOIN bit in OTGFS_GINTSTS register), clear the
INCOMPISOIN interrupt; For any synchronous IN endpoint, when Odd/Even bits match the
current frame number bit 0, and when the endpoint remains enabled, the controller generates an
interrupt at the end of the frame. This interrupt is generated on one of the following conditions:
(1) There is no token in a frame
(2) Late data write to the receive FIFO. An IN token has arrived before the completion of data write
(3) IN token error
The INCOMPISOIN interrupt in the OTGFS_GINTSTS register is a global interrupt. Therefore, when
more than one synchronous endpoints are in active state, the application must determine which one of
the synchronous IN endpoints has not yet completed data transfers.
To achieve this, read the DSTS and DIEPCTLx bits of all synchronous endpoints. If the current endpoing
has been enabled, and the read value of the SOFFN bit in the OTGFS_DSTS register is equal to the
target frame number of the endpoint, it indicates that this endpoint has not finished data transfers. The
application must keep track of nd update the target frame number of the synchronous endpoint.
If data transfer is not yet complete on an endpoint, then Odd/Even bits have to be toggled.
Next:
(1) When the DPID is set to 1 (an odd frame) in the OTGFS_DIEPCTLx register, write 1 to the SETD0PID
bit in the OTGFS_DIEPCTLx register makes it an even frame, then data transmission starts when there
is an IN token input in the next frame.
(2) When the DPID is set to 0 in the OTGFS_DIEPCTLx register, write 1 to the SETD1PID bit in the
OTGFS_DIEPCTLx register makes it an odd frame, then data transmission starts when there is an IN
token input in the next frame.
20.5.4.18
Incomplete synchronous OUT data transfers
To initialize the controller after power-on reset, the application must perform the steps list in OTGFS
Initializtion. Before communicating with a host, the controller must follow the steps defined in Endpoint
Initializtion to initialize endpoints. This section describes the application programming sequence when
the controller drops synchronous OUT data packets.
【
Internal data flow
】
1. For synchronous OUT endpoints, the XFERC interrupt (in the OTGFS_DOEPINTx register) may not
always be generated. If the controller drops synchronous OUT data packets, the application may fail
to detect the XFERC interrupt in the OTGFS_DOEPINTx register.
When the receive FIFO cannot accommodate the complete ISO OUT data packet, the controller
drops the received ISO OUT data.
When the synchronous OUT data packet is received with CRC errors.
When the synchronous OUT token received by the controller is corrupted.
When the application is very slow in reading the receive FIFO
2. When the controller detects the end of periodic frames before transfer complete to all synchronous
OUT endpoints, an interrupt of incomplete synchronous OUT data is generated, indicating that an
XFERC interrupt in the OTGFS_DOEPINTx register is not set on at least one of the synchronous OUT
endpoints. At this point, the endpoint with the incomplete data transfer remains enabled, but no valid
transfers are in progress on this endpoint.
【
Application programming sequence
】
1. The assertion of the incomplete synchronous OUT data interrupt indicates that at least one
synchronous OUT endpoint has an incomplete data transfer in the current frame.
2. If this occurs because the synchronous OUT data is not completely read out from the endpoint, the
application must empty all synchronous OUT data (data and status) in the receive FIFO before
proceeding.
When all data are read from the receive FIFO, the application can detect the XFERC interrupt in
the OTGFS_DOEPINTx register. In this case, the application must re-enable the endpoint to
