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AT32WB415
Series Reference Manual
2022.04.13
Page 344
Ver 2.00
20.6.4.2 OTGFS host frame interval register ( OTGFS_HFIR)
This register is used to program the frame interval at current enumeration speed.
Bit
Register
Reset value
Type
Description
Bit 31: 17 Reserved
0x0000
resd
Kept at its default value.
Bit 16
HFIRRLDCTRL
0x0
rw
Reload control
This bit is used to disable/enable dynamic reload for the
host frame register at runtime.
1: Reload control disable
0: Reload control enable
This bit must be configured at initialization. Do not change
its value at runtime.
Bit 15: 0
FRINT
0xEA60
rw
Frame interval
The application uses this filed to program the interval
between two consecutive SOFs (full speed)
The number of PHY locks in this field indicates the frame
interval. The application can write a value to the host frame
interval register only after the port enable bit in the host
port control and status register has been set.
If no value is programmed, the controller calculates the
value based on the PHY clock frequency defined in the
FS/LS PHY clock select bit of the host configuration
register. Do not change the value of this field after initial
configuration.
1 ms * (FS/LS PHYPHY clock frequency) - 1
20.6.4.3 OTGFS host frame number/frame time remaining register
(OTGFS_HFNUM)
This register indicates the current frame number,and also the time remaining in the current frame (in
terms of the number of PHY clocks).
Bit
Register
Reset value
Type
Description
Bit 31: 16 FTREM
0x0000
ro
Frame time remaining
Indicates the time remaining in the current frame (FS/HS),
in terms of the number of PHY clocks. This field
decrements with the number of PHY clocks. When it
reaches zero, this filed is reloaded with the value of the
frame interval register, and a new SOF is transmiited on
the USB bus.
Bit 15: 0
FRNUM
0x3FFF
ro
Frame number
This field increments every time a new SOP is transmitted
on the USB bus, and is cleared to 0 when the value
reaches 16'h3FFF.
20.6.4.4 OTGFS host periodic Tx FIFO/request queue register
(OTGFS_HPTXSTS)
This is a ready-only register containing the free space information of the perioid Tx FIFO and the periodic
transmit request queue.
Bit
Register
Reset value
Type
Description
Bit 31: 24 PTXQTOP
0x00
ro
Top of the periodic transmit request queue)
Indicates that the MAC is processing the request from the
perioic tranmit request queue. This register is used for
debugging.
Bit [31]: Odd/Even frame
0: Transmit in even frame
1: Transmit in odd frame
Bit [30: 27]: Channel/Endpoint number
Bit [26: 25]: Type
00: IN/OUT
01: Zero-length packet
10: Reserved
11: Channel command disable
Bit [24]: Terminate (last request for the selected channel or