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AT32WB415
Series Reference Manual
2022.04.13
Page 62
Ver 2.00
5
Flash memory controller (FLASH)
5.1 FLASH introduction
Flash memory is divided into three parts: main Flash memory, information block and Flash memory
registers.
Main Flash memory is up to 256 KB
Information block consists of 18 KB boot loader and the user system data area. The boot loader
uses USART1, USART2 or OTGFS device mode for ISP programming.
Main Flash memory contains bank 1 only (256 KB), including 128 pages, 2K per page.
Table 5-1
Flash memory architecture(256 K)
Bank
Name
Address range
Main memory
Bank1
(256 KB)
Page 0
0x0800 0000 – 0x0800 07FF
Page 1
0x0800 0800 – 0x0800 0FFF
Page 2
0x0800 1000 – 0x0800 17FF
…
…
Page 127
0x0803 F800 – 0x0803 FFFF
Information block
18 KB boot loader
0x1FFF AC00 – 0x1FFF F3FF
1 KB user system data
0x1FFF F800 – 0x1FFF FBFF
User system data area
The system data will be read from the information block of Flash memory whenever a system reset
occurs, and is saved in the user system data register (FLASH_USD)and erase programming protection
status register (FLASH_EPPS).
Each system data occupies two bytes, where the low bytes corresponds to the contents in the system
data area, and the high bytes represent the inverse code that is used to verify the correctness of the
selected bit. When the high byte is not equal to the inverse code of the low byte (except when both high
and low byte are all 0xFF), the system data loader will issue a system data error flag (USDERR) and the
corresponding system data and their inverse codes are forced 0xFF.
Note: The update of the contents in the user system data area becomes effective only after a
system reset.
Table 5-2
User system data area
Address
Bit
Description
0x1FFF_F800
[7: 0]
FAP[7: 0]: Flash memory access protection (Access protection
enable/disable result is stored in the FLASH_USD[1] register and bit
[26]
0xA5: Flash access protection disabled
0XCC: High-level Flash access protection enabled
Others; Low-level Flash access protection enabled
[15: 8]
nFAP[7: 0]: Inverse code of FAP[7: 0]
[23: 16]
SSB[7:0]: System configuration byte (it is stored in the FLASH_USD[9:
2] register)
Bit 7: 3
Reserved
Bit 2 (nSTDBY_RST)
0: Reset occurs when entering Standby
mode
1: No reset occurs when entering
Standby mode
Bit 1 (nDEPSLP_RST)
0: Reset occurs when entering
Deepsleep mode
1: No reset occurs when entering
Deepsleep mode
Bit 0 (nWDT_ATO_EN)
0: Watchdog is enabled
1: Watchdog is disabled
[31: 24]
nSSB[7: 0]: Inverse code of SSB[7: 0]
0x1FFF_F804
[7: 0]
Data0[7: 0]: User data 0 (It is stored in the FLASH_USD[17:10]
register)
[15: 8]
nData0[7: 0]: Inverse code of Data0[7: 0]