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AT32WB415
Series Reference Manual
2022.04.13
Page 140
Ver 2.00
register will clear the TDC bit; This bit can also be cleared by writing “0”, but this is valid only in
DMA mode.
12.8 Receiver
12.8.1 Receiver introduction
USART receiver has its individual REN control bit (bit 2 in the USART_CTRL1 register). The
transmitter and receiver share the same baud rate that is programmable. There is a receive data buffer
(RDR) and a receive shift register in the USART.
The data is input on the RX pin of the USART. When a valid start bit is detected, the receiver ports the
data received into the receive shift register in LSB mode. After a full data frame is received, based on
the programmed frame format, it will be moved from the receive shift register to the receive data buffer,
and the RDBF is set accordingly. An interrupt is generated if the RDBFIEN is set.
If hardware flow control is selected, the control signal is output on the RTS pin.
During data reception, the USART receiver will detect whether there are errors to occur, including
framing error, overrun error, parity check error or noise error, depending on software configuration, and
whether there are interrupts to generate using the interrupt enable bits.
12.8.2 Receiver configuration
Configuration procedure:
1. USART enalbe: UEN bit is set.
2. Full-
duplex/half-duplex configuration: Refer to full-duplex/half-duplex selector for more information.
3. Mode
configuration: Refer to mode selector for more information.
4. F
rame format configuration: Refer to frame format for more information.
5. In
terrupt configuration: Refer to interrupt generation for more information.
6. Reception using DMA:
If the DMA mode is selected, the DMAREN bit is set, and configure DMA
register accordingly.
7. Baud
rate configuration: Refer to baud rate generation for details.
8. Receiver
enable: REN bit is set.
Character repeption:
The RDBF bit is set. It indicates that the content of the shift register is transferred to the RDR
(Receiver Data Register). In other words, data is received and can be read (including its
associated error flags)
An interrupt is generated when the RDBFIEN is set.
The erro flag is set when a framing error, noise error or overrun error is detected during
reception.
In DMA mode, the RDNE bit is set after every byte is received, and it is cleared when the data
register is read by DMA.
In non-DMA mode, the RDBF bit is cleared when read access to the USART_DT register by
software. The RDBF flag can also be cleared by writing 0 to it. The RDBF bit must be cleared
before the end of next frame reception to avoid overrun error.
Break frame reception:
Non-LIN mode: It is handled as a framing error, and the FERR is set. An interrupt is generated if
the corresponding interrupt bit is enabled. Refer to framing error decribed below for details.
LIN mode: It is handled as a break frame, and the BFF bit is set. An interrupt is generated if the
BFIEN is set.
Idle frame reception:
It is handled as a data frame, and the IDLEF bit is set. An interrupt is generated if the IDLEIEN is
set.
When a framing error occurs: