AT32WB415
Series Reference Manual
2022.04.13
Page 138
Ver 2.00
12.4 USART frame format and configuration
USART data frame consists of start bit, data bit and stop bit, with the last data bit being as a parity bit.
USART idle frame size is equal to that of the data frame under current configuration, but all bits are 1.
USART break frame size is the current data frame size plus its stop bit. All bits before the stop bit are 0.
The DBN bit is used to program 8-bit (DBN=0) or 9-bit (DBN=1) data bits.
The STOPBN bit is used to program one bit (STOPBN=00), 0.5-bit (STOPBN=01), 2-bit (STOPBN=10)
and 1.5-bit (STOPBN=11) stop bits.
Set the PEN bit will enable parity control. PSEL=1 indicates Odd parity, while PSEL=0 for Even parity.
Once the parity control is enabled, the MSB of the data bit will be replaced with parity bit, that is, the
significant bits is reduced by one bit.
12.5 DMA transfer introduction
Enable transmit data buffer and receive data buffer using DMA to achieve continuous high-speed
transmission for USART, which is detailed in subsequent sections. For more information on specific DMA
configuration, refer to DMA chapter.
12.5.1 Transmission using DMA
1.
Select a DMA channel: Select a DMA channel from DMA channel map table described in DMA
chapter.
2.
Configure the destination of DMA transfer: Configure the USART_DT register address as the
destination address bit of DMA transfer in the DMA control register. Data will be sent to this address
after transmit request is received by DMA.
3.
Configure the source of DMA transfer: Configure the memory address as the source of DMA transfer
in the DMA control register. Data will be loaded into the USART_DT register from the memory
address after transmit request is received by DMA.
4.
Configure the total number of bytes to be transferred in the DMA control register
(TMRx_DMACTRL).
5.
Configure the channel priority of DMA transfer in the DMA control register (TMRx_DMACTRL).
6.
Configure DMA interrupt generation after half or full transfer in the DMA control register
(TMRx_DMACTRL).
7.
Enable DMA transfer channel in the DMA control register (TMRx_DMACTRL).
12.5.2 Reception using DMA
1.
Select a DMA transfer channel: Select a DMA channel from DMA channel map table described in
DMA chapter.
2.
Configure the destination of DMA transfer: Configure the memory address as the destination of DMA
transfer in the DMA control register. Data will be loaded from the USART_DT register to the
programmed destination after reception request is received by DMA.
3.
Configure the source of DMA transfer: Configure the USART_DT register address as the source of
DMA transfer in the DMA control register. Data will be loaded from the USART_DT register to the
programmed destination after reception request is received by DMA.
4.
Configure the total number of bytes to be transferred in the DMA control register
(TMRx_DMACTRL).
5.
Configure the channel priority of DMA transfer in the DMA control register (TMRx_DMACTRL).
6.
Configure DMA interrupt generation after half or full transfer in the DMA control register
(TMRx_DMACTRL).
7.
Enable a DMA transfer channel in the DMA control register (TMRx_DMACTRL).
