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ARTERY AT32WB415 Series, Reference Manual

The ARTERY AT32WB415 Series is a cutting-edge electronic device that revolutionizes connectivity. To learn more about its features and specifications, make sure to download the free Reference Manual from our website. This manual provides step-by-step instructions on how to maximize the performance of your ARTERY device.

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  AT32WB415

 

Series  Reference  Manual

 

2022.04.13

 

Page 132 

 

Ver 2.00

 

0: The data is being transferred from the DT register to the 
shift register (the data is still loaded with the data at this 
point.) 
1: The data has been moved from the DT register to the 
shift register. The data register is empty now.   
This flag is set when the DT register is empty, and cleared 
when writing to the DT register. 
Note: The TDBE bit is not cleared by writing the first data 
to be transmitted, or by writing data when the TDC is set, 
since the data register is still empty at this time. 

Bit 6 

RDBF 

0x0 

ro 

Receive data buffer full flag 
0: Data register is empty. 
1: Data register is full (data received) 
This flag is cleared when the DT register is read. 
The RDBF bit is not set at ARLOST event. 

Bit 5 

Reserved 

0x0 

resd 

Kept at its default value. 

Bit 4 

STOPF 

0x0 

ro 

Stop condition generation complete flag 
0: No Stop condition is detected. 
1: Stop condition is detected. 
This  bit  is  set  by  hardware  when  a  Stop  condition  is 
detected on the bus by the slave if ACKEN=1. 
It is cleared by reading STS1 register followed by writing 
to the CTRL1 register. 

Bit 3 

ADDRHF 

0x0 

ro 

Master 9~8 bit address head match flag 
0: Master 9~8 bit address head mismatch 
1: Master 9~8 bit address head match 
Set by hardware when the first byte is sent by master in 
10-bit address mode. 
Cleared by a write to the CTRL1 register after the STS1 
register is read by software, or by hardware when PEN=0. 
Note: The ADDR10 bit is not set after a NACK reception. 

Bit 2 

TDC 

0x0 

ro 

Data transfer complete flag 
0: Data transfer is not completed yet (the shift register still 
holds data) 
1: Data transfer is completed (shift register is empty) 
This bit is cleared automatically by read or write access to 
the  DT  reginser,  or  when  a  Start  or  Stop  condition  is 
received. 
When STRETCH=0 
In reception mode, when a new byte (including ACK pulse) 
is received and the data register is not read yet (RDBF=1) 
In  transmission mode,  when  a  new  byte  is  sent  and the 
data register is not written yet (TDBE=1) 
The TDC is set under both conditions. 

Bit 1 

ADDR7F 

0x0 

ro 

0~7 bit address match flag 
0: Address  is  not  sent  in  host  ode  or  received  in  slave 
mode 
1: Address is sent in host mode or address is received in 
slave mode. 
Cleared by read access to STS2 register after the software 
reads STS1 register. 
Note: the ADDR7F bit is not set after a NACK reception. 

Bit 0 

STARTF 

0x0 

ro 

Start condition generation complete flag 
0: No Start condition is generated. 
1: Start condition is generated. 
Cleared by write access to the DT register after the 

Summary of Contents for AT32WB415 Series

Page 1: ...Clock and reset management CRM External master clock input Internal 48 MHz factory trimmed clock HICK accuracy 1 at TA 25 C 2 5 at TA 40 to 105 C with automatic clock calibration ACC PLL with configu...

Page 2: ...6 1 3 1 Flash memory size register 36 1 3 2 Device electronic signature 36 2 Memory resources 37 2 1 Internal memory address map 37 2 2 Flash memory 38 2 3 SRAM memory 38 2 4 Peripheral address map 38...

Page 3: ...3 6 APB peripheral clock enable register CRM_AHBEN 55 4 3 7 APB2 peripheral clock enable register CRM_AHB2EN 56 4 3 8 APB1 peripheral clock enable register CRM_AHB1EN 57 4 3 9 Battery powered domain c...

Page 4: ...register FLASH_ADDR 75 5 7 7 User system data register FLASH_USD 75 5 7 8 Erase program protection status register FLASH_EPPS 76 5 7 9 Flash security library status register0 SLIB_STS0 76 5 7 10 Flas...

Page 5: ...er GPIOx_CLR x A F 83 6 3 7 GPIO write protection register GPIOx_WPR x A F 83 7 Multiplexed function I Os IOMUX 84 7 1 Introduction 84 7 2 Functional overview 84 7 2 1 IOMUX structure 84 7 2 2 MUX Inp...

Page 6: ...8 3 EXINT registers 98 8 3 1 Interrupt enable register EXINT_INTEN 98 8 3 2 Event enable register EXINT_EVTEN 98 8 3 3 Polarity configuration register1 EXINT_ POLCFG1 98 8 3 4 Polarity configuration r...

Page 7: ...2 10 2 2 Common data register CRC_CDT 112 10 2 3 Control register CRC_CTRL 113 10 2 4 Initialization register CRC_IDT 113 11 I2 C interface 114 11 1 I2C introduction 114 11 2 I2C main features 114 11...

Page 8: ...6 1 Introduction 139 12 6 2 Configuration 139 12 7 Transmitter 139 12 7 1 Transmitter introduction 139 12 7 2 Transmitter configuration 139 12 8 Receiver 140 12 8 1 Receiver introduction 140 12 8 2 R...

Page 9: ...58 13 3 2 SPI control register2 SPI_CTRL2 159 13 3 3 SPI status register SPI_STS 160 13 3 4 SPI data register SPI_DT 160 13 3 5 SPICRC register SPI_CPOLY 161 13 3 6 SPIRxCRC register SPI_RCRC 161 13 3...

Page 10: ...4 17 DMA control register TMRx_DMACTRL 183 14 1 4 18 DMA data register TMRx_DMADT 183 14 2 General purpose timer TMR9 to TMR11 184 14 2 1 TMRx introduction 184 14 2 2 TMRx main features 184 14 2 2 1...

Page 11: ...TMR1 introduction 203 14 3 2 TMR1 main features 203 14 3 3 TMR1 functional overview 203 14 3 3 1 Count clock 203 14 3 3 2 Counting mode 205 14 3 3 3 TMR input function 208 14 3 3 4 TMR output functio...

Page 12: ...DT 227 15 1 WWDT introduction 227 15 2 WWDT main features 227 15 3 WWDT functional overview 227 15 4 Debug mode 228 15 5 WWDT registers 228 15 5 1 Control register WWDT_CTRL 228 15 5 2 Configuration r...

Page 13: ...4 17 4 8 ERTC alarm clock A register ERTC_ALA 244 17 4 9 ERTC alarm clock B register ERTC_ALB 245 17 4 10 ERTC write protection register ERTC_WP 245 17 4 11 ERTC subsecond register ERTC_SBS 245 17 4 1...

Page 14: ...56 18 5 ADC registers 256 18 5 1 ADC status register ADC_STS 257 18 5 2 ADC control register1 ADC_CTRL1 257 18 5 3 ADC control register2 ADC_CTRL2 258 18 5 4 ADC sampling time register 1 ADC_SPT1 260...

Page 15: ...eceive FIFO 1 register CAN_RF1 282 19 7 1 6 CAN interrupt enable register CAN_INTEN 283 19 7 1 7 CAN error status register CAN_ESTS 284 19 7 1 8 CAN bit timing register CAN_BTMG 285 19 7 2 CAN mailbox...

Page 16: ...tialization 292 20 5 2 OTGFS FIFO configuration 293 20 5 2 1 Device mode 293 20 5 2 2 Host mode 294 20 5 2 3 Refresh controller transmit FIFO 295 20 5 3 OTGFS host mode 295 20 5 3 1 Host initializatio...

Page 17: ...registers 326 20 6 1 CSR register map 326 20 6 2 OTGFS register address map 328 20 6 3 OTGFS global registers 330 20 6 3 1 OTGFS status and control register OTGFS_GOTGCTL 330 20 6 3 2 OTGFS interrupt...

Page 18: ...348 20 6 4 10OTGFS host channelx interrupt mask register OTGFS_HCINTMSKx x 0 8 where x channel number 349 20 6 4 11 OTGFS host channelx transfer size register OTGFS_HCTSIZx x 0 8 where x channel numb...

Page 19: ...number 362 20 6 5 18 OTGFS device IN endpoint transmit FIFO status register OTGFS_DTXFSTSx x 1 3 where x is endpoint number 363 20 6 5 19 OTGFS device OUT endpoint x transfer size register OTGFS_DOEPT...

Page 20: ...AT32WB415 Series Reference Manual 2022 04 13 Page 20 Ver 2 00 22 4 2 DEBUG control register DEBUG_CTRL 371 23 Revision history 373...

Page 21: ...al interrupt Event controller block diagram 97 Figure 9 1 DMA block diagram 100 Figure 9 2 Re arbitrae after request acknowledge 101 Figure 9 3 PWIDTH byte MWIDTH half word 102 Figure 9 4 PWIDTH half...

Page 22: ...el 1 to 4 168 Figure 14 16 C1ORAW toggles when counter value matches the C1DT value 169 Figure 14 17 Upcounting mode and PWM mode A 169 Figure 14 18 Up down counting mode and PWM mode A 170 Figure 14...

Page 23: ...hannel 1 input stage 208 Figure 14 59 Channel output stage channel 1 to 3 209 Figure 14 60 Channel 4 output stage 209 Figure 14 61 C1ORAW toggles when counter value matches the C1DT value 210 Figure 1...

Page 24: ...ailboxes 285 Figure 20 1 Block diagram of OTGFS structure 290 Figure 20 2 OTGFS interrupt hierarchy 292 Figure 20 3 Writing the transmit FIFO 297 Figure 20 4 Reading the receive FIFO 297 Figure 20 5 H...

Page 25: ...5 DMA flexible request sources 104 Table 9 6 DMA register map and reset value 105 Table 10 1 CRC register map and reset value 112 Table 11 1 I2 C register map and reset values 127 Table 12 2 Data samp...

Page 26: ...TC register map and reset values 239 Table 18 1 Trigger sources for ADC 252 Table 18 2 ADC register map and reset values 256 Table 19 1 CAN register map and reset values 275 Table 20 1 OTGFS input out...

Page 27: ...ation interfaces such as SPI I2C USART UART CAN bus controller USB2 0 full speed interface 12 bit ADC programmable voltage monitor PVM and other peripherals Cortex M4 processer supports enhanced high...

Page 28: ...Flash Controller Flash SRAM APB2 Bridge APB1 Bridge APB2 Bus Freq Max 75 MHz APB1 Bus Freq Max 75 MHz CRM TMR2 TMR4 TMR5 ERTC WWDT PWC USART2 USART3 UART5 CAN BPR WDT IOMUX EXINT TMR1 USART1 I2 C1 TMR...

Page 29: ...SWJ DP ROM Table WIC Interrupts and Power control SW JTAG SBUS DBUS IBUS 1 1 2 Bit band With the help of bit band read and write access to a single bit can be performed using common load store operat...

Page 30: ...ed into a bit band address first For a read operation read one word in the bit band region and then move the targeted bit to the right to LSB before returning LSB For a write opearation first move the...

Page 31: ...u just need do Read the bit status from the bit band alias region Compare and jump Apart from making code more concise its important function is also reflected in multi task environment When it comes...

Page 32: ...rupt 0x0000_006C 12 19 Configu rable DMA channel 2 DMA channel 2 global interrrupt 0x0000_0070 13 20 Configu rable DMA channel 3 DMA channel 3 global interrrupt 0x0000_0074 14 21 Configu rable DMA cha...

Page 33: ...x0000_0104 50 57 Configu rable TMR5 TMR5 global interrupt 0x0000_0108 51 58 Reserved 0x0000_010C 52 59 Reserved 0x0000_0110 53 60 Configu rable UART5 UART5 global interrupt 0x0000_0114 54 61 Reserved...

Page 34: ...e instructions from the address corresponding to this value Figure 1 5 Reset process reset Fetch MSP Fetch reset vector Fetch 1st instruction Read address 0x0000_0000 Read address 0x0000_0004 Read res...

Page 35: ...mory from which CODE starts BOOT1 BOOT0 00 10 CODE starts from the main Flash memory BOOT1 BOOT0 11 CODE starts from Boot code BOOT1 BOOT0 11 CODE starts from SRAM After a system reset or when leaving...

Page 36: ...event resd Reserved 1 3 Device characteristics information Table 1 5 List of abbreviations for registers Register abbr Base address Reset value F_SIZE 0x1FFF F7E0 0xXXXX UID 31 0 0x1FFF F7E8 0xXXXX X...

Page 37: ...g Aliased to Flash or system memory according to BOOT pins configuration 0x0000_0000 0x07FF_FFFF 0x0800_0000 Flash Memory 0x0803_FFFF Reserved 0x0804_0000 0x1FFF_AC00 Boot Memory User System Data 0x1F...

Page 38: ...ser system data 0x1FFF F800 0x1FFF FBFF 2 3 SRAM memory The AT32WB415 series contain a 32 KB on chip SRAM which starts at the address 0x2000_0000 It can be accessed by bytes half words 16 bit or words...

Page 39: ...FF EXINT 0x4001 0000 0x4001 03FF IOMUX APB1 0x4000 8000 0x4000 FFFF Reserved 0x4000 7C00 0x4000 7FFF Reserved 0x4000 7800 0x4000 7BFF Reserved 0x4000 7400 0x4000 77FF Reserved 0x4000 7000 0x4000 73FF...

Page 40: ...00 2000 0x4000 23FF Reserved 0x4000 1C00 0x4000 1FFF Reserved 0x4000 1800 0x4000 1BFF Reserved 0x4000 1400 0x4000 17FF Reserved 0x4000 1000 0x4000 13FF Reserved 0x4000 0C00 0x4000 0FFF TMR5 timer 0x40...

Page 41: ...ied through a VBAT pin Figure 3 1 Block diagram of each power supply Wake Up Logic I O Ring VSSA VREF From 2 4 V up to VDDA VREF VDD VDDA VSS VSSA VSS VDD VBAT LDO POR VDD Power domain 1 2v Power doma...

Page 42: ...gure 3 2 Power on reset Low voltage reset waveform Reset VDD VLVR VPOR Temporization tRESTTEMPO VPOR VLVR hysteresis 3 4 Power voltage monitor PVM The PVM is used to monitor the power supply variation...

Page 43: ...l not be disconnected from VBAT because of the VDD being at its rising phrase or due to VDD low voltage reset If the power switch has not been switched to the VDD when the VDD is powered on quickly it...

Page 44: ...pt generated on any external interrupt line in Event mode can wake up the system from Deepsleep mode When the MCU exits the Deepsleep mode the HICK RC oscillator is enabled and selected as a system cl...

Page 45: ...eading this bit at any time will return all zero Bit 2 CLSWEF 0 wo Clear SWEF flag 0 No effect 1 Clear the SWEF flag Note Clear the SWEF flag after two system clock cycles This bit is cleared by hardw...

Page 46: ...are enter Standby mode and cleared by POR LVR or by setting the CLSEF bit Bit 0 SWEF 0 ro Standby wake up event flag 0 No wakeup event occurred 1 A wakeup event occurred Note This bit is set by hardwa...

Page 47: ...has a maximum of 150 MHz and both APB1 and APB2 are up to 75 MHz 4 1 1 Clock sources High speed external oscillator HEXT An external clock source can be provided by HEXT bypass Its frequency can be up...

Page 48: ...0 5 MHz N 2 3 4 5 ERTC clock sources HEXT 128 oscillator LEXT oscillator and LICK oscillator Once the clock source is selected it cannot be altered without resetting the battery powered domain If the...

Page 49: ...is type of reset is enabled when entering Standby mode by clearing the nSTDBY_RST bit in the user system data area this type of reset is also enabled when entering Deepsleep mode by clearing the nDEPS...

Page 50: ...esd Kept at its default value Bit 25 PLLSTBL 0x0 ro PLL clock stable This bit is set by hardware after PLL is ready 0 PLL clock is not ready 1 PLL clock is ready Bit 24 PLLEN 0x0 rw PLL enable This bi...

Page 51: ...ed by software It can also be set by hardware when exiting Standby or Deepsleep mode When a HEXT clock failure occurs This bit can also be set When the HICK is used as the sytem clock this bit cannot...

Page 52: ...ivided by 8 111 divided by 16 Note The software must set these bits correctly to ensure that the APB2 clock frequency does not exceed 75 MHz Bit 10 8 APB1DIV 0x0 rw APB1 division The divided HCLK is u...

Page 53: ...BLF 0 No effect 1 Clear Bit 16 LICKSTBLFC 0x0 wo LICK stable flag clear Writing 1 by software to clear LICKSTBLF 0 No effect 1 Clear Bit 15 13 Reserved 0x0 resd Kept at its default value Bit 12 PLLSTB...

Page 54: ...0x0 rw USART1 reset 0 Does not reset USART1 1 Reset USART1 Bit 13 Reserved 0x0 resd Kept at its default value Bit 12 Reserved 0x0 resd Kept at its default value Bit 11 TMR1RST 0x0 rw TMR1 reset 0 Does...

Page 55: ...RT2 1 Reset USART2 Bit 16 15 Reserved 0x0 resd Kept at its default value Bit 14 SPI2RST 0x0 rw SPI2 reset 0 Does not reset SPI2 1 Reset SPI2 Bit 13 12 Reserved 0x0 resd Kept at its default value Bit 1...

Page 56: ...fault value Bit 20 TMR10EN 0x0 rw TMR10 clock enable 0 Disabled 1 Enabled Bit 19 TMR9EN 0x0 rw TMR9 clock enable 0 Disabled 1 Enabled Bit 18 15 Reserved 0x0 resd Kept at its default value Bit 14 USART...

Page 57: ...22 Reserved 0x0 resd Kept at its default value Bit 21 I2C1EN 0 rw I2C1 clock enable 0 Disabled 1 Enabled Bit 20 USART5EN 0x0 rw USART5 clock enable 0 Disabled 1 Enabled Bit 19 Reserved 0x0 resd Kept a...

Page 58: ...s reset 00 No clock 01 LEXT 10 LICK 11 HEXT 128 Bit 7 3 Reserved 0x00 resd Kept at its default value Bit 2 LEXTBYPS 0x0 rw Low speed external crystal bypass 0 Disabled 1 Enabled Bit 1 LEXTSTBL 0x0 ro...

Page 59: ...sd Kept at its default value 4 3 12 PLL configuration register CRM_PLL Access 0 wait state by words half words and bytes Bit Name Reset value Type Description Bit 31 PLLCFGEN 0x0 rw PLL configuration...

Page 60: ...KCAL_KEY 0x00 rw HICK calibration key The HICKCAL 7 0 can be written only when this field is set 0x5A 4 3 14 OTG_FS extended control register CRM_OTG_EXTCTRL The application must program this register...

Page 61: ...ce it is enabled the AHB bus is halted by hardware till the completion of the switch During this switch period the DMA remain working and the interrupt events are recorded and then handled by NVIC whe...

Page 62: ...gh bytes represent the inverse code that is used to verify the correctness of the selected bit When the high byte is not equal to the inverse code of the low byte except when both high and low byte ar...

Page 63: ...used to protect page48 page61 of main Flash memory Each bit takes care of 2 KB pages Bit 7 is used to protect the page 62 and the remaining pages as well as main Flash memory extension area 0 Erase w...

Page 64: ...sed in the FLASH_ADDR register Set the SECERS and ERSTR bit in the FLASH_CTRL register to enable page erase Wait until the OBF bit becomes 0 in the FLASH_STS register Read the EPPERR bit and ODF bit i...

Page 65: ...nd ODF bit in the FLASH_STS register to verify the erased pages Note 1 When the boot loader code area is configured as the Flash memory extension area performing mass erase operation erases automatica...

Page 66: ...omes 0 read the EPPERR PRGMERR and ODF bit to verify the programming result Note 1 When the address to be written is not erased in advance the programming operation is not executed unless the data to...

Page 67: ...D_UNLOCK register the USDULKS bit in the FLASH_CTRL register will be automatically set by hardware indicating that it supports write erase operation to the user system data area Note Writing an incorr...

Page 68: ...ck the OBF bit in the FLASH_STS register to confirm that there is no other programming operation in progress Set the USDPRGM bit in the FLASH_CTRL register so that the programming instructions for the...

Page 69: ...igure 5 5 System data area programming process OBF 0 Set the USDPRGM bit 1 in FLASH_CTRL Write word half word 32bits 16 bits data No Yes Start Check the OBF bit in FLASH_STS No Check the OBF bit in FL...

Page 70: ...er a system reset Once enabled it cannot be unlocked and it is not permissible for users to re erase and write the system data area Note 1 The main memory extension area can also be protected 2 If the...

Page 71: ...for every customer Security library helps prevent from deliberate damage or changing terminal application codes Note Security library can only be located in the main Flash memory Security library cod...

Page 72: ...of Flash memory after successful configuration as follows Read the bit 0 in the SLIB_STS0 register to obtain the current mode of the bootloader code area Write the value 0xA35F6D24 to the SLIB_UNLOCK...

Page 73: ...16C 0x0000 0000 SLIB_UNLOCK 0x170 0x0000 0000 5 7 1 Flash performance select register FLASH_PSR Bit Abbr Reset value Type Description Bit 31 6 Reserved 0x00000 resd Kept at its default value Bit 5 PFT...

Page 74: ...its default value Bit 2 PRGMERR 0 rw1c Programming error When the programming addess is not 0xFFFF this bit is set by hardware It is cleared by writing 1 Bit 1 Reserved 0 resd Kept at its default valu...

Page 75: ...erase It indicates sector erase operation Bit 0 FPRGM 0 rw Flash program It indicates Flash program operation 5 7 6 Flash address register FLASH_ADDR Bit Register Reset value Type Description Bit 31...

Page 76: ...s set it indicates that the main Flash memory is partially or completely depending on the setting of SLIB_STS1 used as security library code Bit 2 EM_SLIB_ENF 0 ro Extension memory sLib enable flag Wh...

Page 77: ...R 0 ro Security library password error This bit is set by hardware when the password is incorrect and the setting value of the password clear register is different from 0xFFFF FFFF Note When this bit...

Page 78: ...y and return 0 when being read 5 7 17 Security library address setting register SLIB_SET_RANGE For Flash security library address setting only Bit Register Reset value Type Description Bit 31 22 SLIB_...

Page 79: ...e bits are write only and return no response when being read 5 7 19 Boot mode setting register BTM_MODE_SET For boot loader code area only Bit Register Reset value Type Description Bit 31 8 Reserved 0...

Page 80: ...oftware Each pin can be configured as external interrupt input Each pin can be locked 6 2 Functional overview 6 2 1 GPIO structure Each of the GPIO pins can be configured by software as four input mod...

Page 81: ...1 IOMC 0 ODT register Push Pull 00 001 Output mode large sourcing sinking strength 010 Output mode normal sourcing sinking strength 011 Output mode normal sourcing sinking strength 1xx Output mode Ma...

Page 82: ...m sourcing sinking strength Note Some port registers have different reset values 6 3 2 GPIO configuration register high GPIOx_CFGHR x A F Bit Register Reset value Type Description Bit 31 30 Bit 27 26...

Page 83: ...nged which acts as ODT register bit operations 0 No action to the correspoinding ODT bits 1 Set the correspoinding ODT bits 6 3 6 GPIO bit clear register GPIOx_CLR x A F Bit Register Reset value Type...

Page 84: ...down input To enable multiplexed function output the port must be configured as multiplexed function output mode push pull or open drain by setting GPIOx_CFGLR or GPIOx_CFGHR register In this case the...

Page 85: ...number of the desired peripheral IOMUX functions in different packages Pin mapping is achieved by setting the IOMUX_REMAP and IOMUX_REMAPx registers Table 7 1 IOMUX output configuration Mode IOFC HDR...

Page 86: ...by other peripherals To utilize more pins during this period the above mentioned remap configuration can be changed by setting the SWJTAG_MUX 2 0 bit in the IOMUX_REMAP register and SWJTAG_GMUX 2 0 b...

Page 87: ...0 0000 IOMUX_REMAP4 0x24 0x0000 0000 IOMUX_REMAP5 0x28 0x0000 0000 IOMUX_REMAP6 0x2C 0x0000 0000 IOMUX_REMAP7 0x30 0x0000 0000 IOMUX_REMAP8 0x34 0x0000 0000 Note IOMUX clock must be enabled before rea...

Page 88: ...on TMR8_TRGO Bit 17 ADC1_ETP_MUX 0x0 rw ADC1 external trigger preempted conversion multiplexing This bit is used to select external trigger input for ADC1 preempted conversion 1 ADC1 external trigger...

Page 89: ...external interrupt configuration register1 IOMUX_EXINTC1 Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 12 EXINT3 0x0000 rw EXINT3 input sou...

Page 90: ...D pin7 0100 GPIOF pin7 Others Reserved Bit 11 8 EXINT6 0x0000 rw EXINT6 input source configuration Select the input source for EXINT6 external interrupt 0000 GPIOA pin6 0001 GPIOB pin6 0010 GPIOC pin6...

Page 91: ...served Bit 11 8 EXINT10 0x0000 rw EXINT10 input source configuration Select the input source for EXINT10 external interrupt 0000 GPIOA pin10 0001 GPIOB pin10 0010 GPIOC pin10 0011 GPIOD pin10 0100 GPI...

Page 92: ...ce configuration Select the input source for EXINT13 external interrupt 0000 GPIOA pin13 0001 GPIOB pin13 0010 GPIOC pin13 0011 GPIOD pin13 0100 GPIOF pin13 Others Reserved Bit 3 0 EXINT12 0x0000 rw E...

Page 93: ...ng 0 TMR5_CH4 is connected to PA3 1 LICK is connected to TMR5_CH4 to get calibration Bit 18 16 TMR5_GMUX 0x0 rw TMR5 IO general multiplexing Select IO multiplexing for TMR4 0000 CH1 PA0 CH2 PA1 CH3 PA...

Page 94: ...ers Unused Bit 3 0 Reserved 0x0 resd Kept at its default value 7 3 11 IOMUX remap register6 IOMUX_REMAP6 Bit Register Reset value Type Description Bit 31 28 Reserved 0x0 resd Kept at its default value...

Page 95: ...s GPIO 010 Supports SWD But JTAG is disabled PA15 PB3 PB4 can be used as GPIO 100 SWD and JTAG are disabled All SWJTAG pins canbe used as GPIO Others No effect Bit 15 10 Reserved 0x00 resd Kept at its...

Page 96: ...4 11 Either CMP output signal or TMR2_GMUX IO signal is connected to TMR2 channel 4 Bit 3 2 TMR1_CH1_ CMP_GMUX 0x0 rw TMR1 channel 1 internal mapping 00 01 TMR1_GMUX IO signal is connected to TMR1 ch...

Page 97: ...s bit on each interrupt Each interrupt can be cleared independently 8 2 Function overview and configuration procedure With up to 23 interrupt lines EXINT_LINE 19 0 EXINT can detect not only GPIO exter...

Page 98: ...0 EXINT_EVTEN 0x04 0x0000 0000 EXINT_ POLCFG1 0x08 0x0000 0000 EXINT_ POLCFG2 0x0C 0x0000 0000 EXINT_ SWTRG 0x10 0x0000 0000 EXINT_ INTSTS 0x14 0x0000 0000 8 3 1 Interrupt enable register EXINT_INTEN...

Page 99: ...0000 rw Software triggle on line x If the corresponding bit in EXINT_INTEN register is 1 the software writes to this bit The hardware sets the corresponding bit in the EXINT_INTSTS automatically to ge...

Page 100: ...es AMBA compliant Rev 2 0 Only support AHB OKAY and ERROR responses HBUSREQ and HGRANT of AHB master interface are not supported Support 7 channels Peripheral to memory memory to peripheral and memory...

Page 101: ...ular mode the contents in the DMA_CxDTCNT register is automatically reloaded with the initially programmed value after the completion of the last transfer Memory to memory mode M2M This mode indicates...

Page 102: ...MWIDTH half word B3 B2 B1 B0 Half word3 Half word2 Half word1 Half word0 4th 3rd 2nd 1st B3 B2 B1 B0 4th 3rd 2nd 1st HW3 HW2 HW1 HW0 AHB Read Sequence AHB Write Sequence Figure 9 4 PWIDTH half word MW...

Page 103: ...tivated by setting the control bits in the corresponding peripheral registers Table 9 3 DMA1 requests for each channel Periphe rals Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel...

Page 104: ...eserved 47 reserved 48 reserved 49 reserved 50 reserved 51 reserved 52 reserved 53 TMR1_TRIG 54 TMR1_HALL 55 TMR1_OVERFLOW 56 TMR1_CH1 57 TMR1_CH2 58 TMR1_CH3 59 TMR1_CH4 60 reserved 61 TMR2_TRIG 62 r...

Page 105: ...x0000 0000 DMA_C3PADDR 0x38 0x0000 0000 DMA_C3MADDR 0x3C 0x0000 0000 DMA_C4CTRL 0x44 0x0000 0000 DMA_C4DTCNT 0x48 0x0000 0000 DMA_C4PADDR 0x4C 0x0000 0000 DMA_C4MADDR 0x50 0x0000 0000 DMA_C5CTRL 0x58...

Page 106: ...vent occurred Bit 21 FDTF6 0x0 ro Channel 6 transfer complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 20 GF6 0x0 ro Channel 6 global event flag 0 No tra...

Page 107: ...r complete event flag 0 No transfer complete event occurred 1 Transfer complete event occurred Bit 4 GF2 0x0 ro Channel 2 global event flag 0 No transfer error half transfer or transfer complete event...

Page 108: ...sfer flag clear 0 No effect 1 Clear the HDTF5 flag in the DMA_STS register Bit 17 FDTFC5 0x0 rw1c Channel 5 transfer complete flag clear 0 No effect 1 Clear the FDTF5 flag in the DMA_STS register Bit...

Page 109: ...ffect 1 Clear the DTERRF1 flag in the DMA_STS register Bit 2 HDTFC1 0x0 rw1c Channel 1 half transfer flag clear 0 No effect 1 Clear the HDTF1 flag in the DMA_STS register Bit 1 FDTFC1 0x0 rw1c Channel...

Page 110: ...ccessible by bytes half words or words Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit 15 0 CNT 0x0000 rw Number of data to transfer The number o...

Page 111: ...for more information Bit 15 8 CH2_SRC 0x00 rw CH2 source select When DMA_FLEX_EN 1 channel 2 is selected by the CH2_SRC Refer to Section 9 3 8 for more information Bit 7 0 CH1_SRC 0x00 rw CH1 source...

Page 112: ...e Perform write read operation through CRC_DT register Set an initialization value with the CRC_IDT register The value is loaded into CRC_DT register after each CRC reset 10 2CRC registers CRC_DT regi...

Page 113: ...is used to control how to reverse input data 00 No effect 01 Byte reverse 10 Half word reverse 11 Word reverse Bit 4 1 Reserved 0x0 resd Kept at its default value Bit 0 RST 0x0 rw Reset CRC calculatio...

Page 114: ...Programmable digital noise filter Support SMBus2 protocol PEC generation and verification SMBus reminder capability ARP address resolution protocol Timeout detection PMBus 11 3I2C function overview I...

Page 115: ...e and slave mode Switching from master mode to slave mode vice versa is supported as well By default the interface operates in slave mode When GENSTART 1 is set Start condition is activated the I2 C b...

Page 116: ...ting data 5 Clock stretching capability Clock stretching is enabled by setting the STRETCH bit in the I2C_CTRL1 register Once enabled when the slave cannot process data in a timely manner on certain c...

Page 117: ...Data2 A DataN NA P EV2 EV3 EV4 EV3 EV3 SCL Stretch 7 bit address 10 bit address R W 0 R W 1 R W 7 bit address mode 1 Wait for the master to send addresses 2 EV1 Address is matched ADDR7F 1 and then t...

Page 118: ...RL1 register will clear the event EV1 EV2 EV3 RDBF Address Head S A Address A SCL Stretch Data1 A Data2 A DataN A P EV2 EV3 EV1 7 bit address 10 bit address EV2 EV2 EV2 EV2 0 R W 0 R W 11 4 2 I2 C mas...

Page 119: ...tretch SCL Stretch EV1 EV1 EV3 7 bit address mode 1 Generate a Start condition GENSTART 1 2 EV1 Start condition is ready STARTF 1 Read STS1 and write the address to DT register 3 EV2 Address is matche...

Page 120: ...ave to Master RS Repeated Start S Start A Acknowledge P Stop Example I2C Master receive N bytes from I2C Slave EV1 I2C_STS1_STARTF 1 reading STS1 and write the address to I2C_DT will clear the event E...

Page 121: ...Figure 11 7 Transfer sequence of master receiver when N 2 Address S 1 A Data1 A SCL Stretch Data2 A DataN NA P Master to Slave Slave to Master RS Repeated Start S Start A Acknowledge P Stop Example I...

Page 122: ...r receiving the byte and it is cleared when the I2C_DT register is read 10 End of communication 3 When I2C interrupt priority is not very high but the number of bytes to receive is equal to 2 Set the...

Page 123: ...clearing ADDR7F bit the master enters receive state at this time 8 EV3 TDC 1 set GENSTOP 1 and then read the I2C_DT register twice 9 End of communication 4 When I2C interrupt priority is not very hig...

Page 124: ...complete interrupt bit The DATAIEN bit in the I2C_CTRL2 register must be set 0 when using DMA for data transfer The following sequence is for data transfer with DMA Transmission using DMA 1 Set the p...

Page 125: ...us is in Idle state or not as long as a parameter is input while running on a certain transmission speed without the need of detecting the STOP signals one after another or even keeping STOP and other...

Page 126: ...x 2 Enable ALERT interrupt if necessary an interrupt is generated when receiving ARA address 3 Wait until the host gets the slave addresses through ARA 4 Report its own address but it continues to wai...

Page 127: ...N Timeout error TMOUT PEC error PECERR Overload underload OUF Acknowledge failure ACKFAIL Arbitration lost ARLOST Bus error BUSERR 11 4 6 I2 C debug mode When the microcontroller enters debug mode Cor...

Page 128: ...1 ACKEN bit controls ACK of the next byte to be transferred This bit is used only when the number of bytes to receive is equal to 2 so as to ensure that the host responds to ACK in time Bit 10 ACKEN...

Page 129: ...second GENSTART GENSTP or PECTEN request may be set 11 5 2 Control register2 I2C_CTRL2 Bit Register Reset value Type Description Bit 15 13 Reserved 0x0 resd Forced to be 0 by hardware Bit 12 DMAEND 0x...

Page 130: ...dress 2 7 bit address Bit 0 ADDR2EN 0x0 rw Own address 2 enable 0 In 7 bit address mode only OADDR1 is recognized 1 In 7 bit address mode both OADDR1 and OADDR2 are recognized 11 5 5 Data register I2C...

Page 131: ...error 1 PEC error occurs This bit is cleared by software Bit 11 OUF 0x0 rw0c Overload underload flag In transmission mode 0 Normal 1 Underload In reception mode 0 Normal 1 Overload This bit is cleare...

Page 132: ...g 0 Master 9 8 bit address head mismatch 1 Master 9 8 bit address head match Set by hardware when the first byte is sent by master in 10 bit address mode Cleared by a write to the CTRL1 register after...

Page 133: ...is not received 1 General call address is received Cleared when a Stop Start condition is received or by hardware when I2CEN 0 Bit 3 Reserved 0x0 resd Keep at its default value Bit 2 DIRF 0x0 ro Trans...

Page 134: ...ODE 0 High level SPEED x TI2C_CLK x 1 Low level SPEED x TI2C_CLK x 2 DUTYMODE 1 High level SPEED x TI2C_CLK x 9 Low level SPEED x TI2C_CLK x 16 The minimum value allowed in standard mode is 4 In fast...

Page 135: ...standard and CTS RTS Clear To Send Request To Send hardware flow operation It also allows mutli processor communication and supports silent mode waken up by idle frames or ID matching to build up a US...

Page 136: ...enerator Shared by transmission and reception up to 9 375 MBits s Programmable frame format Programmable data word length 8 bits or 9 bits Programmable stop bits support 1 or 2 stop bits Programmable...

Page 137: ...on such configuration method along with that of receiver and transmitter described in the subsequent sections are used to make USART initialization configuration 1 LIN mode While LINEN bit is set 1 CL...

Page 138: ...t request is received by DMA 3 Configure the source of DMA transfer Configure the memory address as the source of DMA transfer in the DMA control register Data will be loaded into the USART_DT registe...

Page 139: ...register is empty the data will be moved from the TDR register to the shift register so that the data in the transmit shift register is output on the TX pin in LSB mode The output format depends on th...

Page 140: ...er to mode selector for more information 4 Frame format configuration Refer to frame format for more information 5 Interrupt configuration Refer to interrupt generation for more information 6 Receptio...

Page 141: ...noise detection A start bit detection occurs when the REN bit is set With the oversampling techniques the USART receiver samples data on the 3rd 5th 7th 8th 9th and 10th bits to detect the valid start...

Page 142: ...ver an event when the corresponding interrupt enable bit is set Table 12 3 USART interrupt request Interrupt event Event flag Enable bit Transmit data register empty TDBE TDBEIEN CTS flag CTSCF CTSCFI...

Page 143: ...ransmit data buffer is empty It is cleared by a USART_DT register write operation 0 Data is not transferred to the shift register 1 Data is transferred to the shift register Bit 6 TDC 0x1 rw0c Transmi...

Page 144: ...default value Bit 8 0 DT 0x00 rw Data value This register provides read and write function When transmitting with the parity bit enabled the value written in the MSB bit will be replaced by the parity...

Page 145: ...disabled 1 Interrupt is enabled Bit 3 TEN 0x0 rw Transmitter enable This bit enables the transmitter 0 Transmitter is disabled 1 Transmitter is enabled Bit 2 REN 0x0 rw Receiver enable This bit enabl...

Page 146: ...PHA 0x0 rw Clock phase This bit is used to select the phase of the clock output on the clock pin in synchronous mode or Smartcard mode 0 Data capture is done on the first clock edge 1 Data capture is...

Page 147: ...artcard mode enable 0 Smartcard mode is disabled 1 Smartcard mode is enabled Bit 4 SCNACKEN 0x0 rw Smartcard NACK enable This bit is used to send NACK when parity error occurs 0 NACK is disabled when...

Page 148: ...smartcard mode Bit 7 0 ISDIV 0x00 rw IrDA smartcard division In IrDA mode 8 bit 7 0 is valid It is valid in common mode and must be set to 00000001 In low power mode it divides the peripheral clock t...

Page 149: ...BF ROE RR MM ERR CCE RR TUE RR ACS TDB E RDB F Communication controller CS controlle r SWCSEN SWCSIL SLBEN SLBTD ORA MDIV 3 0 CLKPOL CLKPHA MSTEN Transmitter logic Transmission CRC unit CCEN NTC LTF...

Page 150: ...duplex mode when the SLBEN bit and the ORA bit is both 0 In this case the SPI supports data transmission and reception at the same time IO connection is as follows Figure 13 2 SPI two wire unidirectio...

Page 151: ...OSI pin is released The SLBTD bit is used by software to configure transfer direction When the SLBTD bit is set the SPI can be used only for data transmission when the SLBTD bit is 0 the SPI can be us...

Page 152: ...bit is set the SPIEN and MSTEN bits cannot be set by software The MMERR bit is cleared by read or write access to the SPI_STS register followed by write operation to the SPI_CTRL1 register In slave m...

Page 153: ...ftware receives the last data when the second to last data is received 13 2 6 DMA transfer The SPI supports write and read operations with DMA Refer to the following configuration procedure Special at...

Page 154: ...he TDBE is set After the transmitter is configured and the SPI is enabled the SPI is ready for data transmission Before going forward it is necessary for the users to refer to full duplex half duplex...

Page 155: ...e format select MSB LSB mmode with the LTF bit and select 8 16 bit data with the FBN bit Enable SPI by setting the SPIEN 13 2 9 Motorola mode This section describes the SPI communication timings which...

Page 156: ...gure 13 8 Master half duplex transmit SCK BF flag CS MOSI 1 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 TDBE flag Drive Transmit buffer empty and software can write data Half duplex communication sl...

Page 157: ...ve Configured as follows MSTEN 1 Master enable SLBEN 1 Single line bidirectional mode SLBTD 0 Receive enable CLKPOL 0 CLKPHA 0 SCK idle output low use the first edge for sampling FBN 0 8 bit frame Mas...

Page 158: ...0x10 0x0007 SPI_RCRC 0x14 0x0000 SPI_TCRC 0x18 0x0000 13 3 1 SPI control register1 SPI_CTRL1 Bit Register Reset value Type Description Bit 15 SLBEN 0x0 rw Single line bidirectional half duplex enable...

Page 159: ...ivided by 64 0110 Divided by 128 0111 Divided by 256 1000 Divided by 512 1001 Divided by 1024 Bit 2 MSTEN 0x0 rw Master enable 0 Disabled Slave 1 Enabled Master Bit 1 CLKPOL 0x0 rw Clock polarity Indi...

Page 160: ...itser 0 No mode error 1 Mode error occurs Bit 4 CCERR 0x0 rw0c CRC error Set by hardware and cleared by software 0 No CRC error 1 CRC error occurs Bit 3 TUERR 0x0 ro Transmitter underload error Set by...

Page 161: ...he SPI_CTRL1 register is cleared When the data frame format is set to 8 bit data only the 8 bit LSB 7 0 are calculated based on CRC8 standard when 16 bit data bit is selected follow CRC16 standard Not...

Page 162: ...9 16 Up X 1 65535 X 2 O X X TMR1 0 TMR11 16 Up X 1 65535 X 1 X X X Timer type Timer Counter bit Count mode PWM output Single pulse output Complementary output Dead time Encoder interface connection In...

Page 163: ...utput control Output control Output control Output control C1OUT C2OUT C3OUT C4OUT Polarity selection edge detector prescaler IS3 IS2 IS1 IS0 C21FP1 TMRx_EXT Trigger control Slave mode controller Enco...

Page 164: ...C2IRAW 000 C2IF 2 0 31 32 0 1 2 3 4 Figure 14 5 Block diagram of external clock mode B CK_DIV Slave mode control External clock control EXT Divider Filterr Downcounter Polarity selection Note The dela...

Page 165: ...timer has an internal 16 bit up down up down counter TMR2 5 can be extended to 32 bit by setting the PMEN bit The TMRx_PR register is loaded with the counter value The value in the TMRx_PR is immediat...

Page 166: ..._PR register down to 1 an underflow event is generated and then restarts counting from 0 When the counter counts from 0 to the value of the TMRx_PR register 1 an overflow event is generated and then r...

Page 167: ...3 TMR input function Each of timers TMR2 and TMR5 has four independent channels with each channel being configured as input or output As input the channel can be used for the filtering selection divi...

Page 168: ...omparator and an output controller It is used to program the period duty cycle and polarity of the output signal Figure 14 15 Capture compare channel output stage channel 1 to 4 Output mode controller...

Page 169: ...e and the TMRx_CxDT register will determine the level of CxORAW in advance Figure 14 16 gives an example of output compare mode toggle with C1DT 0x3 When the counter value is equal to 0x3 C1OUT toggle...

Page 170: ...ged until the next overflow event This function can only be used in output capture or PWM modes and does not work in forced mode Figure 14 20 shows the example of clearing CxORAW signal When the EXT i...

Page 171: ...mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input is high and stops as soon as the trigger input is low Figure 14 22 Example of suspend mod...

Page 172: ...counting period TMRx_PR registers Configure the slave timer trigger input signal TRGIN as master timer output STIS 2 0 in the TMRx_STCTRL register Configure the slave timer to use external clock mode...

Page 173: ...re slave timer as trigger mode SMSEL 3 b110 in the TMR2_STCTRL register Figure 14 26 Starting master and slave timers synchronously by an external trigger COUNTER PR 15 0 TMREN TMR_CLK 0 DIV 15 0 32 2...

Page 174: ...Two way counting mode selection 00 One way counting mode depending on the OWCDIR bit 01 Two way counting mode1 count up and down alternately the output flag bit is set only when the counter counts do...

Page 175: ...Register Reset value Type Description Bit 15 ESP 0x0 rw External signal polarity 0 High or rising edge 1 Low or falling edge Bit 14 ECMBEN 0x0 rw External clock mode B enable This bit is used to enabl...

Page 176: ...GIN input 111 External clock mode A Rising edge of the TRGIN input clocks the counter Note Please refer to count mode section for the details on encoder mode A B C 14 1 4 4 DMA interrupt enable regist...

Page 177: ...rigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 Reserved 0x0 resd Kept at its default value Bit 4 C4IF 0x0 rw...

Page 178: ...e Type Description Bit 15 C2OSEN 0x0 rw Channel 2 output switch enable Bit 14 12 C2OCTRL 0x0 rw Channel 2 output control Bit 11 C2OBEN 0x0 rw Channel 2 output buffer enable Bit 10 C2OIEN 0x0 rw Channe...

Page 179: ...irection of the channel 1 input or output and the selection of input pin when C1EN 0 00 Output 01 Input C1IN is mapped on C1IRAW 10 Input C1IN is mapped on C2IRAW 11 Input C1IN is mapped on STCI This...

Page 180: ...election of input pin when C4EN 0 00 Output 01 Input C4IN is mapped on C4IRAW 10 Input C4IN is mapped on C3IRAW 11 Input C4IN is mapped on STCI This mode works only when the internal trigger input is...

Page 181: ...ementary polarity Defines the active edge for input signals refer to C1P for details Bit 6 Reserved 0x0 resd Kept at its default value Bit 5 C2P 0x0 rw Channel 2 polarity Pleaser refer to C1P descript...

Page 182: ...rw Channel 1 data register When TMR2 or TMR5 enables plus mode the PMEN bit in the TMR_CTRL1 register the C1DT is expanded to 32 bits Bit 15 0 C1DT 0x0000 rw Channel 1 data register When the channel...

Page 183: ...When the channel 4 is configured as input mode The C4DT is the CVAL value stored by the last channel 4 input event C1IN When the channel 4 is configured as output mode C4DT is the value to be compare...

Page 184: ...ent trigger event and channel event Figure 14 27 Block diagram of general purpose TMR9 C1IFP1 C2IFP2 prescaler Output control Output control C1IRAW C2ORAW C1ORAW C2OUT C1OUT TMRx_CH1 TMRx_CH2 TMRx_CH2...

Page 185: ...CK_INT By default the CK_INT divided by the prescaler is used to drive the counter to start counting Figure 14 29 Control circuit with CK_INT divided by 1 CK_INT TMREN COUNTER 12 11 13 14 15 16 00 01...

Page 186: ...ng trigger signal ISx is not present Figure 14 32 Counter timing with prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A 1B 1C 0 3 00 01 Clear PR 15 0 1C 14 2 3 2 C...

Page 187: ...er C1DT Input mode IC1PS C1EN C1SWTR TMR1_SWEVT Capture Counter C1OBEN C1OBEN OVF From time base unit TMR1_CM1 Comparator Input mode read_in_progress capture_transfer write_in_progress capture_transfe...

Page 188: ...of the TMRx_CxDT register and the corresponding level signal is sent according to the counting direction For more information on PWM mode A B refer to the description of the CxOCTRL 2 0 bit In up dow...

Page 189: ...011 C1OCTRL 2 0 3 C1DT 15 0 Figure 14 39 Upcounting mode and PWM mode A 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31 32 0 1 PR 15 0 C1ORAW TMR_CLK 0 DIV 15 0 32 110 C1OCTRL 2 0 3 C1DT 15 0 C1ORAW 0...

Page 190: ...spend mode 0 1 2 3 4 5 6 7 8 9 COUNTER A B C D 10 PR 15 0 TMR_CLK 0 DIV 15 0 32 101 STIS 2 0 101 SMSEL 2 0 CI1F1 TMR_EN CNT_CLK Slave mode Trigger mode The counter can start counting on the rising edg...

Page 191: ...Reserved 0x00 resd Kept at its default value Bit 9 8 CLKDIV 0x0 rw Clock divider 00 Normal 01 Divided by 2 10 Divided by 4 11 Reserved Bit 7 PRBEN 0x0 rw Period buffer enable 0 Period buffer is disab...

Page 192: ...e mode is disabled 001 Encoder mode A 010 Encoder mode B 011 Encoder mode C 100 Reset mode Rising edge of the TRGIN input reinitializes the counter 101 Suspend mode The counter starts counting when th...

Page 193: ...trigger event occurs 1 Trigger event is generated Trigger event an active edge is detected on TRGIN input or any edge in suspend mode Bit 5 3 Reserved 0x0 resd Kept at its default value Bit 2 C2IF 0x0...

Page 194: ...function in output mode when the channel is in output mode while the CxIx describes its function in output mode when the channel is in input mode Attention must be given to the fact that the same bit...

Page 195: ...re generating an output 1 No need to compare the CVAL and C1DT An output is generated immediately when a trigger event occurs Bit 1 0 C1C 0x0 rw Channel 1 configuration This field is used to define th...

Page 196: ...W 10 Input C1IN is mapped on C2IRAW 11 Input C1IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS 14 2 4 7 Channel control register TMR9_CCTRL Bit Register R...

Page 197: ...it 15 0 DIV 0x0000 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 DIV contains the value written at an overflow event 14 2 4 10 Period register TMR9_PR Bit Register Reset val...

Page 198: ...1 0x00 0x0000 TMRx_IDEN 0x0C 0x0000 TMRx_ISTS 0x10 0x0000 TMRx_SWEVT 0x14 0x0000 TMRx_CM1 0x18 0x0000 TMRx_CCTRL 0x20 0x0000 TMRx_CVAL 0x24 0x0000 TMRx_DIV 0x28 0x0000 TMRx_PR 0x2C 0x0000 TMRx_C1DT 0x...

Page 199: ...el 1 interrupt flag If the channel 1 is configured as input mode This bit is set by hardware on a capture event It is cleared by software or read access to the TMRx_C1DT 0 No capture event occurs 1 Ca...

Page 200: ...e TMRx_C1DT TMRx_CVAL else low OWCDIR 1 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high 111 PWM mode B OWCDIR 0 C1ORAW is low once TMRx_ C1DT TMRx_CVAL else high OWCDIR 1 C1ORAW is high once TMRx_ C...

Page 201: ...t capture is generated at each active edge 01 An input compare is generated every 2 active edges 10 An input compare is generated every 4 active edges 11 An input compare is generated every 8 active e...

Page 202: ...14 2 5 8 Division value TMRx_DIV Bit Register Reset value Type Description Bit 15 0 DIV 0x0000 rw Divider value The counter clock frequency fCK_CNT fTMR_CLK DIV 15 0 1 DIV contains the value written a...

Page 203: ...ansfer Figure 14 44 Block diagram of advanced control timer Input filter C2IFP1 C1IFP1 XOR Prescaler Output control Output control Output control Output control C4IRAW C3IRAW C2IRAW C4ORAW C3ORAW C2OR...

Page 204: ...ock diagram of external clock mode A EXT C1IFP2 C1IFP1 C1INC ISx CK_DIV Trigger select Slave mode control External clock control CI1RAW Filter Edge detector C2IF_Rising C2IF_Falling Polarity selection...

Page 205: ...th prescaler value changing from 1 to 4 TMR_CLK CK_CNT COUNTER OVFIF DIV 15 0 18 17 19 1A 1B 1C 0 3 00 01 Clear PR 15 0 1C 14 3 3 2 Counting mode The advanced control timer consists of a 16 bit counte...

Page 206: ...nternal clock divided by 4 TMR_CLK CNT_CLK COUNTER OVFIF 0 1 2 3 4 DIV 15 0 32 31 30 32 PR 15 0 Clear Up down counting mode In up down counting mode the counter counts up down alternatively When the c...

Page 207: ...b001 3 b010 3 b011 In this mode the two inputs C1IN C2IN are required Depending on the level on one input the counter counts up or down on the edge of the other input The OWCDIR bit indicates the dir...

Page 208: ...signal is detected and the capture compare interrupt flag bit CxIF is set An interrupt DMA request will be generated if the CxIEN bit and CxDEN bit are enabled If the selected trigger signal is detect...

Page 209: ...the CxDT register The counter value is compared with the value of the TMRx_CxDT register and the corresponding level signal is sent according to the counting direction For more information on PWM mod...

Page 210: ...B The counter only counts only one cycle and the output signal sents only one pulse Figure 14 61 C1ORAW toggles when counter value matches the C1DT value 0 1 2 3 31 32 0 1 2 3 31 32 0 1 2 3 COUNTER 31...

Page 211: ...7 CxDT EXT CxORAW Dead time insertion The channel 1 to 3 of the advanced control timers contains a set of reverse channel output This function is enabled by the CxCEN bit and its polarity is defined...

Page 212: ...ve state depending on the polarity This is done asynchronously so that it works even if no clock is provided to the timer If the timer clock is still active then the dead time generator is activated T...

Page 213: ...CLK 0 DIV 15 0 32 101 STIS 2 0 OVFIF TRGIF 100 SMSEL 2 0 Slave mode Suspend mode In this mode the counter is controlled by a selected trigger input The counter starts counting when the trigger input i...

Page 214: ...MR1_CVAL 0x24 0x0000 TMR1_DIV 0x28 0x0000 TMR1_PR 0x2C 0x0000 TMR1_RPR 0x30 0x0000 TMR1_C1DT 0x34 0x0000 TMR1_C2DT 0x38 0x0000 TMR1_C3DT 0x3C 0x0000 TMR1_C4DT 0x40 0x0000 TMR1_BRK 0x44 0x0000 TMR1_DMA...

Page 215: ...x0 resd Kept at its default value Bit 14 C4IOS 0x0 rw Channel 4 idle output state Bit 13 C3CIOS 0x0 rw Channel 3 complementary idle output state Bit 12 C3IOS 0x0 rw Channel 3 idle output state Bit 11...

Page 216: ...d by 2 10 Divided by 4 11 Divided by 8 Bit 11 8 ESF 0x0 rw External signal filter This field is used to filter an external signal The external signal can be sampled only after it has been generated N...

Page 217: ...LLDE 0x0 rw HALL DMA request enable 0 Disabled 1 Enabled Bit 12 C4DEN 0x0 rw Channel 4 DMA request enable 0 Disabled 1 Enabled Bit 11 C3DEN 0x0 rw Channel 3 DMA request enable 0 Disabled 1 Enabled Bit...

Page 218: ...TRGIN input or any edge in suspend mode Bit 5 HALLIF 0x0 rw0c HALL interrupt flag This bit is set by hardware on HALL event It is cleared by writing 0 0 No Hall event occurs 1 Hall event is detected...

Page 219: ...ffect 1 Generate an overflow event 14 3 4 7 TMR1 channel mode register1 TMR1_CM1 The channel can be used in input capture mode or output compare mode The direction of a channel is defined by the corre...

Page 220: ...ediately In PWM mode A or B this bit is used to accelerate the channel 1 output s response to the trigger event 0 Need to compare the CVAL with C1DT before generating an output 1 No need to compare th...

Page 221: ...output compare mode The direction of a channel is defined by the corresponding CxC bits All the other bits of this register have different functons in input and output modes The CxOx describes its fu...

Page 222: ...n C3EN 0 00 Output 01 Input C3IN is mapped on C3IRAW 10 Input C3IN is mapped on C4IRAW 11 Input C3IN is mapped on STCI This mode works only when the internal trigger input is selected by STIS 14 3 4 9...

Page 223: ...CxORAW xor CxP Cx_EN 1 Output disabled no driven by the timer CxCOUT 0 CxCEN 0 0 1 1 CxORAW polarity dead time Cx_EN 1 CxORAW inverted polarity dead time CxCEN 1 1 0 0 Output disabled no driven by the...

Page 224: ...r Reset value Type Description Bit 15 0 RPR 0x00 rw Repetition of period value This field is used to reduce the generation rate of overflow events An overflow event is generated when the repetition co...

Page 225: ...Type Description Bit 15 OEN 0x0 rw Output enable This bit acts on the channels as output It is used to enable CxOUT and CxCOUT outputs 0 Disabled 1 Enabled Bit 14 AOEN 0x0 rw Automatic output enable...

Page 226: ...an all be write protected Thus it is necessary to configure write protection when writing to the TMRx_BRK register for the first time 14 3 4 19 TMR1 DMA control register TMR1_DMACTRL Bit Register Rese...

Page 227: ...r Figure 15 1 Window watchdog block diagram EN 7 bit window value WIN 6 0 Prescaler 1 2 4 8 7 bit counter CNT 6 0 PCLK 4096 CNT 0x40 reset reload at CNT WIN reset To prevent sytem reset the counter mu...

Page 228: ...d the WWDT counter stops counting by setting the WWDT_PAUSE in the DEBUG module Refer to Chapter 30 2 for more information 15 5WWDT registers These peripheral registers must be accessed by word 32 bit...

Page 229: ...ided by 8192 10 PCLK1 divided by 16384 11 PCLK1 divided by 32768 Bit 6 0 WIN 0x7F rw Window value if the counter is reloaded while its value is greater than the window register value a reset is genera...

Page 230: ...tten with the value 0xAAAA at regular intervals to reload the counter value to avoid the WDT reset WDT write protected The WDT_DIV and WDT_RLD registers are write protected Writing the value 0x5555 to...

Page 231: ...D 0x08 0x0000 0FFF WDT_STS 0x0C 0x0000 0000 16 5 1 Command register WDT_CMD Reset in Standby mode Bit Register Reset value Type Description Bit 31 16 Reserved 0x0000 resd Kept at its default value Bit...

Page 232: ...can be read only when RLDF 0 16 5 4 Status register WDT_STS Reset in Standby mode Bit Register Reset value Type Description Bit 31 2 Reserved 0x0000 0000 resd Kept at its default value Bit 1 RLDF 0x0...

Page 233: ...tion supporting time stamp feature Supports fine and coarse calibration 20 x battery powered registers 5 x interrupts alarm A B periodic auto wakeup tamper detection and time stamp Multiplexed functio...

Page 234: ...protection After a power on reset all ERTC registers are write protected Such protection mechanism is not affected by the system reset Write access to the ERTC registers except the ERTC_STS 14 8 ERTC...

Page 235: ...ed before setting the ERTC_TADJ register Reference clock detection and coarse digital calibration cannot be used at the same time Thus when RCDEN 1 coarse digital calibration is not supported Reading...

Page 236: ...nsumption modes automatically The period is programmed with the VAL 15 0 bi When WATCLK 2 1 it is extended to 17 bits and the wakeup counter value is VAL 216 When the wakeup counter value drops from t...

Page 237: ...e is being updated Once the calibration value is successfully applied this bit is cleared automatically indicating the completion of the calibration value update 17 3 5 Reference clock detection The c...

Page 238: ...FLT 00 2 Select tamper detection valid level TP1EDG 3 Select tamper detection sampling frequency through the TPFREQ bit 4 According to your needs enable tamper detection pull up setting TPPU 1 When TP...

Page 239: ...utomatic wakeup Time stamp Tamper event LICK Alarm clock A Alarm clock B Periodic automatic wakeup Time stamp Tamper event LEXT Alarm clock A Alarm clock B Periodic automatic wakeup Time stamp Tamper...

Page 240: ...mat only It is 0 for 24 hr format instead Bit 21 20 HT 0x0 rw Hour tens Bit 19 16 HU 0x0 rw Hour units Bit 15 Reserved 0x0 resd Kept at its default value Bit 14 12 MT 0x0 rw Minute tens Bit 11 8 MU 0x...

Page 241: ...bit when the hour is being incremented Bit 16 ADD1H 0x0 wo Add 1 hour 0 No effect 1 Add 1 hour Note The next second takes effect when this bit is set don t set this bit when the hour is being incremen...

Page 242: ...is in progress This bit is automatically set when software writes to the ERTC_SCAL register It is automatically cleared when a new calibration value is taking into account When this bit is set the wr...

Page 243: ...filed ERTC_DATE is different from 0 It is cleared when the year is 0 Bit 3 TADJF 0x0 ro Time adjustment flag 0 No time adjustment 1 Time adjustment is in progress This bit is automatically set when a...

Page 244: ...31 MASK4 0x0 rw Date week day mask 0 Date week day is not masked 1 Alarm clock doesn t care about date week day Bit 30 WKSEL 0x0 rw Date week day select 0 Date 1 Week day DT 1 0 is not used Bit 29 28...

Page 245: ...about secondds Bit 6 4 ST 0x0 rw Second tens Bit 3 0 SU 0x0 rw Second units 17 4 10ERTC write protection register ERTC_WP Bit Register Reset value Type Description Bit 31 8 Reserved 0x000000 resd Kept...

Page 246: ...7 6 Reserved 0x0 resd Kept at its default value Bit 5 4 DT 0x0 ro Date tens Bit 3 0 DU 0x0 ro Date units Note The content of this register is valid only when the TSF is set in the ERTC_STS register It...

Page 247: ...per detection filter time 0 No filter 1 Tamper is detected after 2 consecutive samples 2 Tamper is detected after 4 consecutive samples 3 Tamper is detected after 8 consecutive samples Bit 10 8 TPFREQ...

Page 248: ...ubsecond register ERTC_ALBSBS Bit Register Reset value Type Description Bit 31 28 Reserved 0x0 resd Kept at its default value Bit 27 24 SBSMSK 0x0 rw Sub second mask 0 No comparison Alarm B doesn t ca...

Page 249: ...AT32WB415 data sheet for more information ADC input range VREF VIN VREF In terms of digital control Regular channels and preempted channels with different priority Regular channels and preempted chann...

Page 250: ...4 GPIO ADC_IN5 ADC_IN10 Input pin description VDDA Analog supply ADC analog supply VSSA Analog supply ground ADC analog supply ground ADCx_IN Analog input signal channels Refer to the AT32WB415 datash...

Page 251: ...cal value 1 2 V is connected to ADC1_IN17 It is required to enable the ITSRVEN bit in the ADC_CTRL2 register before the internal reference channel conversion The converted data of such channel can be...

Page 252: ...d channel conversion is triggered by preempted ones After the OCTEN or PCTEN bit is set in the ADC_CTRL2 register the ADC starts conversion after a trigger source is detected The conversion can be tri...

Page 253: ...n sequence modes are described in the following sections With this the channels can be converted in a specific order 18 4 3 1 Sequence mode The sequence mode is enabled by setting the SQEN bit in the...

Page 254: ...p and preempted group in sequence Figure 18 6 shows an example of the behavior when the repetition mode works with the sequence mode and preempted group auto conversion mode Figure 18 6 Repetition mod...

Page 255: ...N bit in the ADC_CTRL2 register selects the alignment of data right aligned or left aligned Apart from this the converted data of the preempted group is decreased by the offset written in the ADC_PCDT...

Page 256: ...CS preempted channel conversion start flag PCCE preempted channel conversion end flag OCCE ordinary channel conversion end flag and VMOR voltage monitor out of range PCCE CCE and VMOR have their respe...

Page 257: ...eempted group Bit 0 VMOR 0x0 rw0c Voltage monitoring out of range flag This bit is set by hardware and cleared by software writing 0 0 Voltage is within the value programmed 1 Voltage is outside the v...

Page 258: ...ut of range interrupt disabled 1 Voltage monitoring out of range interrupt enabled Bit 5 CCEIEN 0x0 rw Channel conversion end interrupt enable 0 Channel conversion end interrupt disabled 1 Channel con...

Page 259: ...ation occurred or initialization completed 1 Enable initialization or initializationis is ongoing Bit 2 ADCAL 0x0 rw A D Calibration 0 No calibration occurred or calibration completed 1 Enable calibra...

Page 260: ...cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71 5 cycles 111 239 5 cycles Bit 17 15 Reserved 0x00 resd Kept at its default value Bit 14 12 Reserved 0x00 resd Kept at its...

Page 261: ...s 110 71 5 cycles 111 239 5 cycles Bit 14 12 CSPT4 0x0 rw Sample time selection of channel ADC_IN4 000 1 5 cycles 001 7 5 cycles 010 13 5 cycles 011 28 5 cycles 100 41 5 cycles 101 55 5 cycles 110 71...

Page 262: ...xFFF rw Voltage monitoring high boundary 18 5 8 ADC voltage monitor low threshold register ADC_ VWLB Accessed by words Bit Register Reset value Type Description Bit 31 12 Reserved 0x00000 resd Kept at...

Page 263: ...Bit 19 15 OSN4 0x00 rw Number of 4th conversion in ordinary sequence Bit 14 10 OSN3 0x00 rw Number of 3rd conversion in ordinary sequence Bit 9 5 OSN2 0x00 rw Number of 2nd conversion in ordinary sequ...

Page 264: ...0000 rw Conversion data from preempted channel 18 5 14ADC ordinary data register ADC_ ODT Accessed by words Bit Register Reset value Type Description Bit 31 16 ADC2ODT 0x0000 ro ADC2 conversion data o...

Page 265: ...he identifier list mode Supports the identifier mask mode FIFO overrun management Time triggered communication mode 16 bit timers Time stamp on transmission 19 3Baud rate The nominal bit time of the C...

Page 266: ...s performed at the edge location of bit segment 1 and big segment 2 simulatenously During the actual transmission each bit of the CAN nodes has certain phase error due to the oscillator drift transmis...

Page 267: ...ield 2 7 EOF ACK RTR r0 IDE SOF Data frame or remote frame Error frame Inter frame space or overload frame Error flag Error echo Error delimiter 6 6 8 Data frame or remote frame Intermission Suspend t...

Page 268: ...interrupt generation TM0TCF 1 TM1TCF 1 TM2TCF 1 TCIEN 1 TX_INT Figure 19 4 Receive interrupt 0 generation RF0MN 00 RFF0MIEN 1 RF0FF 1 RF0FIEN 1 RF0OF 1 RF0OIEN 1 RX0_INT Figure 19 5 Receive interrupt...

Page 269: ...CAN_FBWCFG and CAN_FRF registers can be modified only when FCS 1 The CAN_FiFBx register can be modified only when FCS 1 or FAENx 0 19 6Functional overview 19 6 1 General description As the number of n...

Page 270: ...s cleared in the CAN_MCTRL register This switch operation is confirmed by hardware clearing the FZC bit in the CAN_MSTS register The CAN controller must be synchronized with the bus Switch to Sleep mo...

Page 271: ...CAN_FiFB1 4 3 CAN_FiFB1 2 0 CAN_FiFB2 31 21 CAN_FiFB2 20 19 CAN_FiFB2 18 16 CAN_FiFB2 15 5 AN_FiFB2 4 3 CAN_FiFB2 2 0 SID 10 0 IDT RTR EID 17 15 SID 10 0 IDT RTR EID 17 15 Filtering mode The filter ca...

Page 272: ...ve Filter number 0 CAN_F0FB1 31 0 ID Yes 0 3 CAN_F3FB1 15 0 ID Yes 0 CAN_F0FB2 31 0 ID 1 CAN_F3FB1 31 16 ID 1 1 CAN_F1FB1 15 0 ID Yes 2 CAN_F3FB2 15 0 ID 2 CAN_F1FB1 31 16 ID 3 CAN_F3FB2 31 16 ID 3 CA...

Page 273: ...to the CAN_FiFBx register i 0 13 x 1 2 Complete the CAN filter configuration by setting FCS 0 in the CAN_FCTRL register 19 6 5 Message transmission Register configuration To transmit a message it is...

Page 274: ...ransmission fails or arbitration is lost if the automatic retransmission mode is disabled the tranmist mailbox become EMPTY if the automatic retransmission mode is enbled the tranmist mailbox becomes...

Page 275: ...s set when an error is detected Error passive flag When either TEC or REC is greater than 127 the system is in the error passive state An error passive flag is set when an error is detected Bus off st...

Page 276: ...X XXXX RFDTL0 1B8h 0xXXXX XXXX RFDTH0 1BCh 0xXXXX XXXX RFI1 1C0h 0xXXXX XXXX RFC1 1C4h 0xXXXX XXXX RFDTL1 1C8h 0xXXXX XXXX RFDTH1 1CCh 0xXXXX XXXX Reserved 1D0h 1FFh xx FCTRL 200h 0x2A1C 0E01 FMCFG 20...

Page 277: ...f mode as soon as an exit timing is detected on the CAN bus When Automatic exit bus off mode is disabled the software must enter leave the freeze mode once more and then the bus off state is left only...

Page 278: ...tus 0 No transmit occurs 1 ransmit is in progress Note This bit is set by hardware when the CAN transmission starts and it is cleared by hardware at the end of transmission Bit 7 5 Reserved 0x0 resd K...

Page 279: ...us register CAN_TSTS Bit Register Reset value Type Description Bit 31 TM2LPF 0x0 ro Transmit mailbox 2 lowest priority flag 0 Mailbox 2 is not given the lowest priority 1 Lowest priority This indicate...

Page 280: ...Bit 17 TM2TSF 0x0 rw1c Transmit mailbox 2 transmission success flag 0 Transmission failed 1 Transmission was successful Note This bit indicates whether the mailbox 2 transmission is successful or not...

Page 281: ...tting by this software has no effect when the mailbox 0 is free Bit 6 4 Reserved 0x0 resd Kept at its default value Bit 3 TM0TEF 0x0 rw1c Transmit mailbox 0 transmission error flag 0 No error 1 Mailbo...

Page 282: ...d 0x0 resd Kept at its default value Bit 1 0 RF0MN 0x0 ro Receive FIFO 0 message num Note These two bits indicate how many messages are pending in the FIFO 0 RF0ML bit is incremented by one each time...

Page 283: ...0 rw Error occur interrupt enable 0 Error interrupt disabled 1 Error interrupt enabled Note The flag bit of this interrupt is the EOIF bit An interrupt is generated when both this bit and EOIF bit are...

Page 284: ...0 rw Transmit mailbox empty interrupt enable 0 Transmit mailbox empty interrupt disabled 1 Transmit mailbox empty interrupt enabled Note The flag bit of this interrupt is the TMxTCF bit An interrupt i...

Page 285: ...the number of time unit in Bit time segment 2 Bit 19 16 BTS1 0x3 rw Bit time segment 1 tBTS1 tCAN x BTS1 3 0 1 Note This field defines the number of time unit in Bit time segment 1 Bit 15 12 Reserved...

Page 286: ...AN_TMCx x 0 2 All the bits in the register are write protected when the mailbox is not in empty state Bit Register Reset value Type Description Bit 31 16 TMTS 0xXXXX rw Transmit mailbox time stamp Not...

Page 287: ...Bit 2 RFIDI 0xX ro Receive FIFO identifier type indication 0 Standard identifier 1 Extended identifier Bit 1 RFFRI 0xX Ro Receive FIFO frame type indication 0 Data frame 1 Remote frame Bit 0 Reserved...

Page 288: ...AN_FMCFG Note This register can be written only when FCS 1 in the CAN_FCTRL register The filter is in configuration mode Bit Register Reset value Type Description Bit 31 14 Reserved 0x00000 resd Kept...

Page 289: ...s CAN_FiFB 2 1 This register can be modified only when the FAENx bit of the CAN_FACFG register is cleared or the FCS bit of the CAN_FCTRL register is set Bit Register Reset value Type Description Bit...

Page 290: ...FS USB 2 0 FS Serial Transceiver USB 2 0 I F GPIO 20 2OTGFS functional description The OTGFS module consists of an OTGFS controller PHY and 1280 byte SRAM The OTGFS supports control transfer bulk tran...

Page 291: ...in the OTGFS_PCFCCTL register 20 3OTGFS clock and pin configuration 20 3 1 OTGFS clock configuration The OTGFS interface has two clocks USB control clock and APB bus clock The USB full speed device b...

Page 292: ...lear an interrupt before unmasking it to avoid servicing an old interrupt 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 7 6 5 4 3 20 5OTGFS functional description 20 5 1 OTGFS initialization If the cable is connect...

Page 293: ...packets If several synchronous endpoints are enabled at least two largest packet size 4 1 spaces are needed to receive data packets In most cases two largest packet size 4 1 spaces are recommended so...

Page 294: ...4 2 spaces must be allocated to receive back to back packets In most cases two largest packet size 4 2 spaces are recommended so that the USB can receive the subseqnet packet while the previous packe...

Page 295: ...OTGFS_GRSTCTL TXFNUM register Set TXFFLSH 0x1 in the OTGFS_GRSTCTL register and wait until it is cleared Set the CGNPINNAK bit in the OTGFS_DCTL register 20 5 3 OTGFS host mode In host mode an extern...

Page 296: ...st Before disabling a channel the application must ensure that there is at least one free space available in the non periodic request queue when disabling a non perioid channel or the periodic request...

Page 297: ...AHBCFG PTXFEMPLVL interrupt Read GNPTXSTS HPTXSIZ registers for available FIFO and queue spaces 1 MPS or LPS FIFO is space available Write 1 packet data to Transmit FIFO More packets to send Start Don...

Page 298: ...f a port babble signal is detected 2 Handling device disconnected conditions If the device is suddently disconnected an interrupt is generated on a disconnect event DISCONINT bit in the OTGFS_GINTSTS...

Page 299: ...a new value 5 New HFIR value takes effect The SOF synchronization resumes after going through above mentioned stpes 20 5 3 7 Initialize bulk and control IN transfers Figure 20 7 shows a typical bulk o...

Page 300: ...t queue once the OTGFS_HCCHAR2 register is written 10 The controller generates an RXFLVL interrupt as soon as the halt status is written to the receive FIFO 11 Read and ignore the receive packet statu...

Page 301: ...it FIFO can store two packets 128 bytes for full speed transfer The non periodic request queue depth is 4 1 OUT SETUP operation process for common bulk and control transfer The sequence of operations...

Page 302: ...his queue can hold 4 entries De allocate ch_1 DATA1 MPS DATA1 write_tx_fifo ch_1 5 set_ch_en ch_2 set_ch_en ch_2 set_ch_en ch_2 read_rx_stsre ad_rx_fifo De allocate ch_2 11 13 1 MPS ch_1 ch_2 ch_2 ch_...

Page 303: ...nitialize interrupt IN transfers Figure 20 8 shows the operation process of a typical interrupt IN transfer Refer to channel 2 ch_2 The assumptions are as follows The application is attempting to rece...

Page 304: ...enerates an XFERC interrupt as soon as the receive packet is read 9 To handle the XFERC interrupt read the PKTCN bit in the OTGFS_HCTSIZ2 register If the PKTCNT bit in the OTGFS_HCTSIZ2 is not equal t...

Page 305: ...ting to send one largest packet size packe transfer size is 64 bytes starting from an odd frame The periodic transmit FIFO can store one packet 1KB bytes for full speed transfer The periodic request q...

Page 306: ...AHB Host USB Device DATA0 MPS DATA0 Periodic Request Queue Assume that this queue can hold 4 entries RXFLVL interrupt write_tx_fifo ch_1 init_reg ch_1 write_tx_fifo ch_1 init_reg ch_1 3 1 MPS 1 MPS D...

Page 307: ...s per packet 1031 bytes for full speed transfer The periodic request queue depth is 4 1 Common interrupt IN operation process The sequence of operations shown in Figure 20 9 channel 2 is as follows 1...

Page 308: ...us IN transfers Unmask XACTERR XFERC FRMOVRUN BBLERR if XFERC or FRMOVRUN if XFERC and HCTSIZx PKTCNT 0 Reset Error Count De allocate Channel else Unmask CHHLTD Disable Channel else if XACTERR or BBLE...

Page 309: ...an example of common synchronous OUT transfers Figure 20 9 Example of common synchronous OUT IN transfers set_ch_en ch_2 set_ch_en ch_2 read_rx_sts read_rx_fifo read_rx_sts init_reg ch_2 init_reg ch_2...

Page 310: ...indicates the end of USB reset Upon receiving this interrupt the application must read the OTGFS_DSTS register to determine the enumeration speed and perform the steps defined in Endpoint initializati...

Page 311: ..._DCFG register with the device address received in the SetAddress command Program the controller to send an IN packet 20 5 4 5 Endpoint initialization on SetConfiguration SetInterface command This sec...

Page 312: ...receive more than 64 byte data during data OUT stage it must re enable the endpoint to receive another 64 byte data and it must contine this operation until the completion of all data reception in da...

Page 313: ...ETUP bit is set in the OTGFS_DOEPINTx register it indicates that a valid SETUP packet has been sent to the application and data stage is initiated see OUT data transfers At the end of the SETUP stage...

Page 314: ...e FIFO the controller triggers a Transfer Completed interrupt on the specified OUT endpoint PKTSTS code can be found in the OTGFS_GRXSTSR OTGFS_GRXSTSP register 6 After the valid data is popped from t...

Page 315: ...ransfer Completed interrupt due to this read operation Internal data flow 1 When a SETUP packet is received the controller writes the received data to the receive FIFO without checking whether there i...

Page 316: ...f this condition occurs the OTGFS controller generates an interrupt B2BSTUP bit in the OTGFS_DOEPINTx register 20 5 4 13 IN data transfers This section describes the internal data flow during IN data...

Page 317: ...Second transfe Transfer size epnum 0x0 Packet count 0x1 2 If an endpoint is enabled for data transfers the controller updates the Transfer size register At the end of the IN transfer indicated by endp...

Page 318: ...and by referring to Read FIFO packets This section describes a regular non synchronous OUT transfers control bulk or interrupt transfers Application requirements 1 For OUT data transfers the transfer...

Page 319: ...with the size of the written packet 6 The OUT data transfer completed mode for an OUT endpoint is written to the receive FIFO one one of the following conditions The transfer size and packet count are...

Page 320: ...ler then triggers the RXFLVL interrupt bit in the OTGFS_GINTSTS register 4 Upon receiving the packet count of USB packets the controller internally sets the NAK bit for the endpoint to prevent it from...

Page 321: ...synchronous OUT data packet read from the receive FIFO Application programming sequence 1 Program the transfer size and the corresponding packet count of the OTGFS_DOEPTSIZx register 2 Program the OTG...

Page 322: ...FS_DIEPINTx register by setting the XFERCMSK bit in the OTGFS_DIEPMSK register 3 Enable synchronous endpoints with the following steps Program the OTGFS_DIEPTSIZx register OTGFS_DIEPTSIZx XFERSIZE n O...

Page 323: ...sion starts when there is an IN token input in the next frame 20 5 4 18 Incomplete synchronous OUT data transfers To initialize the controller after power on reset the application must perform the ste...

Page 324: ...S register The application is slow in writing complete data to the transmit FIFO and an IN token is received before the completion of data write In this case the application can detect the INTKNTXFEMP...

Page 325: ...scheduling of the frame to be transmitted 4 The complete data to be transmitted in a frame must be written to the transmit FIFO by the application before the periodic IN token is received Even when on...

Page 326: ...e USB line 8 The assertion of the XFERC interrupt in the OTGFS_DIEPINTx register with or without the INTKNTXFEMP interrupt indicates the successful completion of an interrupt IN transfer When reading...

Page 327: ...tain OTGFS global register host mode register device mode register data FIFO register power and clock control register 1 OTGFS global registers They are active in both host and device modes The regist...

Page 328: ...00 0200 OTGFS_GNPTXFSIZ OTGFS_DIEPTXF0 0x028 0x0200 0200 OTGFS_GNPTXSTS 0x02C 0x0008 0200 OTGFS_GCCFG 0x038 0x0000 0000 OTGFS_GUID 0x03C 0x0000 1000 OTGFS_HPTXFSIZ 0x100 0x0000 0000 OTGFS_DIEPTXF1 0x1...

Page 329: ...K6 0x5CC 0x0000 0000 OTGFS_HCTSIZ6 0x5D0 0x0000 0000 OTGFS_HCCHAR7 0x5E0 0x0000 0000 OTGFS_HCINT7 0x5E8 0x0000 0000 OTGFS_HCINTMSK7 0x5EC 0x0000 0000 OTGFS_HCTSIZ7 0x5F0 0x0000 0000 OTGFS_HCCHAR8 0x60...

Page 330: ...0000 OTGFS_DOEPCTL3 0xB60 0x0000 0000 OTGFS_DOEPINT3 0xB68 0x0000 0080 OTGFS_DOEPTSIZ3 0xB70 0x0000 0000 OTGFS_PCGCCTL 0xE00 0x0000 0000 OTGFS_DEP3RMPEN 0xD0C 0x0000 0000 OTGFS_USBDIVRST 0xE10 0x0000...

Page 331: ...Description Bit 31 9 Reserved 0x000000 resd Kept at its default value Bit 8 PTXFEMPLVL 0x0 rw Accesible in host mode only Periodic TxFIFO empty level It indicates when the periodic TxFIFO empty interr...

Page 332: ...takes effect Bit 28 15 Reserved 0x0000 resd Kept at its default value Bit 14 Reserved 0x0 resd Kept at its default value Bit 13 10 USBTRDTIM 0x5 rw Accesible in device mode USB Turnaround Time This fi...

Page 333: ...controller is neither writing to nor reading from the TxFIFO Verify using these registers Read NAK effective interrupt NAK Effective Interrupt ensures that the controller is not reading from the FIFO...

Page 334: ...DCFG DECSPD DCTL SFTDIS Resets all state machines except AHB slave to the idle state and clears all the transmit and receive FIFOs All transactions on the AHB master are termindated as soon as possibl...

Page 335: ...connector ID status Bit 27 Reserved 0x0 resd Kept at its default value Bit 26 PTXFEMP 0x1 ro Accesible in host mode only Periodic TxFIFO Empty The interrupt is generated when the Periodic Transmit FI...

Page 336: ...the Device All Endpoints Interrupt register to determine the exact number of the IN endpoint on which the interrupt occurred and then read the corresponding Device IN Endpoint n Interrupt register to...

Page 337: ...vel bit in the Core AHB Configuration register Bit 4 RXFLVL 0x0 ro Accesible in both host and device modes RxFIFO Non Empty Indicates that there is at least one packet to be read from the receive FIFO...

Page 338: ...DISCONINTMSK 0x0 rw Accesible in both host and device modes Disconnect detected interrupt mask Bit 28 CONIDSCHGMSK 0x0 rw Accesible in both host and device modes Connector ID status change mask Bit 27...

Page 339: ...tus Debug Read register returns the data of the top of the Receive FIFO A read to the Receive Status Read and Pop register pops the data of the top of the Receive FIFO The receive status contents are...

Page 340: ...0 SETUP data packet received Others Reserved Bit 16 15 DPID 0x0 ro Data PID Indicates the data PID of the received OUT data packet 00 DATA0 10 DATA1 01 DATA2 11 MDATA Bit 14 4 BCNT 0x000 ro Byte count...

Page 341: ...nly It is a read only register that contains the available space information for the Non periodic TxFIFO and the Non periodic Transmit Request Queue Bit Register Reset value Type Description Bit 31 Re...

Page 342: ...rw Power down This bit is used to activate the transceiver in transmission reception It must be pre configured to allow USB communication 0 Power down enable 1 Power down disable Transceiver active B...

Page 343: ...mode Host mode register are not accessible in device mode as the results are undefined in device mode Host mode registers contain as follows 20 6 4 1 OTGFS host mode configuration register OTGFS_HCFG...

Page 344: ...t frame number frame time remaining register OTGFS_HFNUM This register indicates the current frame number and also the time remaining in the current frame in terms of the number of PHY clocks Bit Regi...

Page 345: ...mask register OTGFS_HAINTMSK The host all channels interrupt mask register OTGFS_HAINTMSK works with the host all channels interrupt register OTGFS_HAINT to interrupt the application when an event oc...

Page 346: ...ther 10 ms to the minimum duration before clearing this bit There is no maximum limit set by the USB standard Bit 7 PRTSUSP 0x0 rw1s Port suspend The application sets this bit to put this port in susp...

Page 347: ...ister This bit can only be set by the controller The application must write 1 to clear this bit Bit 0 PRTCONSTS 0x0 ro Port connect status 0 No device is connected to the port 1 A device is connected...

Page 348: ...ing this register the application must read the host all channels interrupt register to get the exact channel number ofr the host channel n interrupt register The application must clear the correspond...

Page 349: ...mask Bit 0 XFERCMSK 0x0 rw Transfer completed mask 20 6 4 11 OTGFS host channelx transfer size register OTGFS_HCTSIZx x 0 8 where x channel number Bit Register Reset value Type Description Bit 31 Rese...

Page 350: ...register Bit 1 0 DEVSPD 0x0 rw Device speed This field indicates the speed at which the application needs the controller to enumerate or the maximum speed the application can support However the actua...

Page 351: ...numeration Bit 0 RWKUPSIG 0x0 rw Remote wakeup signaling When this bit is set by the application the controller initiates a remote signal to wakeup the USB host The application must set this bit to in...

Page 352: ...register OTGFS_DIEPMSK This register works with each of the device IN endpoint interrupt register for all endpoints to generate an IN endpoint interrupt The IN endpoint interrupt for a specific statu...

Page 353: ...device all endpoints interrupt mask register OTGFS_DAINT When an event occurs on an endpoint The IN OUT endpoint interrupt bits in the OTGS_DAINT register can be used to interrupt the application The...

Page 354: ...smission on the endpoint 0 The controller clears this bit before generating the following interrupts Endpoint disabled Transfer completed Bit 30 EPTDIS 0x0 ro Endpoint disable The application sets thi...

Page 355: ...The controller clears this bit before the generation one of the following interrupts on this endpoing SETUP stage done Endpoint disabled Transfer completed Bit 30 EPTDIS 0x0 rw1s Endpoint disable The...

Page 356: ...ng status 0 The controller is sending non NAK handshakes based on the FIFO status 1 The controller is sending NAK handshakes When this bit is set either by the application or the controller the contro...

Page 357: ...dpoint disabled Transfer completed Bit 30 EPTDIS 0x0 ro Endpoint disable The application cannot disable control OUT endpoint 0 Bit 29 28 Reserved 0x0 resd Kept at its default value Bit 27 SNAK 0x0 wo...

Page 358: ...ollowing interrupts on this endpoint SETUP stage done Endpoint disabled Transfer completed Bit 30 EPTDIS 0x0 ro Endpoint disable The application sets this bit to stop transmitting data on an endpoint...

Page 359: ...based on the FIFO status 1 The controller is sending NAK handshakes When this bit is set either by the application or the controller the controller stops receiving any data on an OUT endpoint even if...

Page 360: ...00 resd Kept at its default value Bit 7 TXFEMP 0x0 ro Transmit FIFO empty This interrupt is generated when the transmit FIFO for this endpint is half or completely empty The half or completely empty s...

Page 361: ...rrent control transfer Upon this interrupt the application can decode the received SETUP data packets Bit 2 Reserved 0x0 resd Kept at its default value Bit 1 EPTDISD 0x0 rw1c Endpoint disabled interru...

Page 362: ...ler decrements this field every time a packet from the receive FIFO is written to the external memory 20 6 5 17 OTGFS device IN endpoint x transfer size register OTGFS_DIEPTSIZx x 1 3 where x is endpo...

Page 363: ...ifies this register The application can only read this register as long as the controller clears the endpoint enable bit Bit Register Reset value Type Description Bit 31 Reserved 0x0 resd Kept at its...

Page 364: ...alue Type Description Bit 31 5 Reserved 0x0000000 resd Kept at its default value Bit 4 SUSPENDM 0x0 ro PHY suspend Indicates that the PHY has been suspended Bit 3 1 Reserved 0x0 resd Kept at its defau...

Page 365: ...R Analog Digital Polarity selection CMP1INVSEL CMP1NINVSEL TM R2_CH4 TM R2_CH_CLR Reserved PA2 PA3 PA7 Reserved PA2 PA5 PA4 VREFINT44 VREFINT34 VREFINT24 VREFINT14 IN 8 TO 1 MUX 4 TO 1 MUX IN CMP2_INV...

Page 366: ...programming and even the CMPxWP can be unlocked only after a system reset This feature can be used for the applications with specific security requirements Low power mode The comparator is clocked by...

Page 367: ...mparator 2 output value is inverted Bit 26 24 CMP2TAG 0x0 rw Comparator output target This field controls the COMP2 output target 000 No selection 001 Timer 1 brake input 010 Timer 1input capture 1 01...

Page 368: ...1 011 Timer 1 output compare clear 100 Timer 2 input capture 4 101 Timer 2 output compare clear 110 Timer 3 input capture 1 111 Timer 3 output compare clear Bit 7 Reserved 0x0 resd Kept at its default...

Page 369: ...d Kept at its default value Bit 17 16 COMP2NINVSEL 0x1 rw Comparator2 non inverting input selection 00 PA7 01 PA3 default 10 PA2 11 Reserved Note This field is read only when CMP2WP 1 Bit 15 2 Reserve...

Page 370: ...Low power mode In Sleep mode the clock programmed by code remains active for HCLK and FCLK to continue to work In DeepSleep mode HICK oscillator is enabled to feed FCLK and HCLK There are several ID...

Page 371: ...U integrates an ID code that is used to identify MCU s revision code The DEBUG_IDCODE register is mapped on the external PPB bus at address 0xE0042000 This code is accessible by the SW debug port or b...

Page 372: ...mode with a data length of 4 Bit 5 TRACE_IOEN 0x0 rw Trace pin assignment enable 0 No trace default state 1 Trace is enabled Bit 4 3 Reserved 0x0 resd Always 0 Bit 2 STANDBY_DEBUG 0x0 rw Debug Standb...

Page 373: ...AT32WB415 Series Reference Manual 2022 04 13 Page 373 Ver 2 00 23 Revision history Document Revision History Date Version Revision Note 2022 04 13 2 00 Initial release...

Page 374: ...ing legal situation in any injudical districts or infringement of any patent copyright or other intellectual property right ARTERY s products are not designed for the following purposes and thus not i...

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