AT32WB415
Series Reference Manual
2022.04.13
Page 237
Ver 2.00
Note: Coarse digital calibration can work correctly only when the DIVA is 6 or above.
Smooth digital calibration:
Smooth digital calibration has a higher and well-distributed performance than the coarse digital
calibration. The calibration is performed by increasing or decreasing ERTC_CLK in an evenly manner.
The smooth digital calibration period is around 2
20
ERTC_CLK (32 seconds) when the ERTC_CLK is
32.768 kHz. The DEC[8: 0] bit specifies the number of pulses to be masked during the 220 ERTC_CLK
cycles. A maximum of 511 pulses can be removed. When the ADD is set, 512 pulses can be inserted
during the 2
20
ERTC_CLK cycles. When DEC[8: 0] and ADD are sued together, a deviation ranging from
-511 to +512 ERTC_CLK cycles can be added during the 2
20
ERTC_CLK cycles.
The effective calibrated frequency (F
SCAL)
:
F
SCAL
= F
ERTC_CLK
× [ 1 +
512
x
ADD
DEC
2
DEC
512
x
ADD
20
]
When the divider A is less than 3, the calibration operates as if ADD was equal to 0. The divider B value
should be reduced so that each second is accelerated by 8 ERTC_CLK cycles, which means that 256
ERTC_CLK cycles are added every 32 seconds. When DEC[8: 0] and ADD are sued together, a
deviation ranging from -255 to +256 ERTC_CLK cycles can be added during the 2
20
ERTC_CLK cycles.
At this point, the effective calibrated frequency (F
SCAL)
F
SCAL
= F
ERTC_CLK
× [ 1 +
256
DEC
2
DEC
256
20
]
It is also possible to select 8 or 16-second digital calibration period through the CAL8 and CAL16 bits.
The 8-second period takes priority over 16-second. In other words, when both 8-second and 16-second
are enabled, 8-second calibration period prevails.
The CALUPDF flag in the ERTC indicates the calibration status. During the configuration of ERTC_SCAL
registers, the CALUPDF bit is set, indicating that the calibration value is being updated; Once the
calibration value is successfully applied, this bit is cleared automatically, indicating the completion of the
calibration value update.
17.3.5 Reference clock detection
The calendar update can be synchronized (not used in low-power modes) to a reference clock (usually
the mains 50 or 60 Hz) with a higher precision. This referece clock is used to calibrate the precision of
the calendar update frequency (1 Hz)
When it is enabled, the reference clock edge detection is performed during the first 7 ck_a periods
around each of the calendar updtes. When detected, the edge is used to update calendar values, and 3
ck_a periods are used for subsequent calendar updates. Each time the reference clock edge is detected,
the divider A value is forced to reload, making the reference clock and the 1 Hz clock are aligned. If the
1 Hz clock has a slight shift, a more accurate reference clock can be used to fine-tune the 1 Hz clock so
that it is aligned with the reference clock. If no reference clock edge is detected, the calendar is updated
based on ERTC’s original clock source.
Note: Once the reference clock detection is enabled, the DIVA and DIVB must be kept at its respective
reset value (0x7F and 0xFF respectively). The clock synchronization cannot be used in conjunction with
the coarse digital calibration.
17.3.6 Time stamp
When time stamp event is detected on the tamper pin (valid edge is detected), the current calendar
value will be stored to the time stamp register.
When a time stamp event occurs, the time stamp flag bit (TSF) in the ERTC_STS register will be set. If
a new time stamp event is detected when time stamp flag (TSF) is already set, then the time stamp
overflow flag (TSOF) will be set, but the time stamp registers will remain the result of the last event. By
setting the TSIEN bit, an interrupt can be generated when a time stamp event occurs.
Usage of time stamp:
1.
How to enable time stamp when a valid edge is detected on a tamper pin
Select a time stamp in by setting the TSPIN bit
