AT32WB415
Series Reference Manual
2022.04.13
Page 318
Ver 2.00
length packets according to the IN token, and the packet count is decremented automatically.
6. If there are no data in the FIFO on a received IN token and the packet count for the endpoint is 0, the
controller generates an “IN token received when FIFO is empty” interrupt, and the NAK bit for the
endpoint is not set. The controller responds with a NAK handshake signal to the non-synchronous
endpoints on the USB.
7. The controller rewinds the FIFO pointers internally and no tiemput interrupt is generated except for
the control IN endpoints.
8. When the transfer size is 0 and the packet count is also 0, the Transfer completed interrupt is
generated and the endpoint enable bit is cleared.
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Application programming sequence
】
1. Program the OTGFS_DIEPTSIZx register according to the transfer size and the corresponding packet
count.
2. Program the OTGFS_DIEPCTLx register according to the endpoint characteristics and set the CNAK
and endpoint enable bits.
3. While sending non-zero-length data packets, the application must poll the OTGFS_DTXFSTSx
register (where n is the FIFO number related to that endpoint) to determine whether there is enough
space in the data FIFO. The application can also use the TXFEMP bit in the OTGFS_DIEPINTx
register before writing data.
20.5.4.15
Non-synchronous OUT data transfers
To initialize the controller after power-on reset, the application must perform the steps list in “OTGFS
Initialization”. Before communicating with a host, the application must initialize endpoints based on the
process described in “Endpoint Initialization” and by referring to “Read FIFO packets”. This section
describes a regular non-synchronous OUT transfers (control, bulk or interrupt transfers).
【
Application requirements
】
1.
For OUT data transfers, the transfer size of the endpoint transfer register must be set to a multiple of
the largest packet size for the endpoint, and adjusted to the DWORD boundary.
if (mps[epnum] mod 4) == 0
transfer size[epnum] = n * (mps[epnum]) //Dword Aligned
else
transfer size[epnum] = n * (mps[epnum] + 4 - (mps[epnum] mod 4)) //Non Dword
Aligned
packet count[epnum] = n
n > 0
2.
Whne an OUT endpoint interrupt occurs, the application must read the endpoint’s transfer size
register to calculate the size of the data in the memory. The received payload size must be less than
the programmed transfer size.
Payload size in memory = Application-programmed initial transfer size – Controller-updated final
transfer size
Number of USB packets the payload was received = Application-programmed initial packet count
– Controller-updated final packet count
【
Internal data flow
】
1. The application must set the transfer size and packet count bits in the endpoint control registers, clear
the NAK bit, and enable the endpoint to receive the data.
2. Once the NAK bit is cleared, the controller starts receiving data and writes it to the receive FIFO as
long as there is available space in the receive FIFO. For each data packet received on the USB line,
the data packet and its status are written to the receive FIFO. The packet count is decremented by 1
each time a packet (largest packet size or a short packet) is written to the receive FIFO.
OUT data packets received with Bad Data CRC are emptied from the receive FIFO
After sending an ACK to the data packet on the USB, the controller discards non-synchronous
OUT data packets that the host (which cannot detect the ACK) re-transmits. The application does
