AT32WB415
Series Reference Manual
2022.04.13
Page 144
Ver 2.00
1: Overflow error is detected.
Note: When this bit iset, the DT regiter content will not be
lost, but the subsequent data will be overwritten.
Bit 2
NERR
0x0
ro
Noise error
This bit is set by hardware when noise is detect on a
received frame. It is cleared by software. (Read
USART_STS register followed by a USART_DT read
operation)
0: No noise is detected.
1: Noise is detected.
Bit 1
FERR
0x0
ro
Framing error
This bit is set by hardware when a stop bit error (low),
excessive noise or break frame is detected. It is cleared by
software. USART_STS register followed by a USART_DT
read operation)
0: No framing error is detected.
1: Framing error is detected.
Bit 0
PERR
0x0
ro
Parity error
This bit is set by hardware when parity error occurs. It is
cleared by software. USART_STS register followed by a
USART_DT read operation)
0: No parity error occurs.
1: Parity error occurs.
12.11.2 Data register (USART_DT)
Bit
Register
Reset value
Type
Description
Bit 31: 9
Reserved
0x000000
resd
Kept at its default value.
Bit 8: 0
DT
0x00
rw
Data value
This register provides read and write function. When
transmitting with the parity bit enabled, the value written in
the MSB bit will be replaced by the parity bit. When
receiving with the parity bit enabled, the value in the MSB
bit is the received parity bit.
12.11.3 Baud rate register (USART_BAUDR)
Note: If the TE or RE is disabled respectively, the baud counter stops counting.
Bit
Register
Reset value
Type
Description
Bit 31: 16 Reserved
0x0000
resd
Kept at its default value.
Bit 15: 0
DIV
0x0000
rw
Divider
This field define the USART divider.
12.11.4 Control register1 (USART_CTRL1)
Bit
Register
Reset value
Type
Description
Bit 31: 14 Reserved
0x00000
resd
Forced to be 0 by hardware.
Bit 13
UEN
0x0
rw
USART enable
0: USART is disabled.
1: USART is enable.
Bit 12
DBN
0x0
rw
Data bit num
This bit is used to program the number of data bits.
0: 8 data bits
1: 9 data bits
Bit 11
WUM
0x0
rw
Wakeup mode
This bit determines the way to wake up silent mode.
0: Waken up by idle line
1: Waken up by ID match
Bit 10
PEN
0x0
rw
Parity enable
This bit is used to enable hardware parity control
(generation of parity bit for transmission; detection of parity
bit for reception). When this bit is enabled, the MSB bit of