AT32WB415
Series Reference Manual
2022.04.13
Page 274
Ver 2.00
Transmit priority configuration
When two or more transmit boxes are in PENDING state, their transmit priority must be given.
By identifier: When MMSSR=0 in the CAN_MCTRL register, the transmit order is defined by the identifier
of the message in the mailbox. The message with lower identifier value has the highest priority. If the
identifier values are the same, the message with lower mailbox number will be transmitted first.
By transmit request order: When MMSSR=1 in the CAN_MCTRL register, the transmit priority is given
by the transmit request order of mailboxes.
Transmit status and error status
The TMxTCF, TMxTSF, TMxALF, TMxTEF and TMxEF bits in the CAN_TSTS register are used to
indicate transmit status and error status.
TMxTCF bit: Transmission complete flag, indicating that the data transmission is complete when
TMxTCF=1.
TMxTSF bit: Transmission success flag, indicating that the data has been transmitted successfully when
TMxTSF =1.
TMxALF bit: Transmission arbitration lost flag, indicating that the data transmission arbitration is lost
when TMxALF=1.
TMxTEF bit: Transmission error flag, indicating that the data transmission failed due to bus error, and
an error frame is sent when TMxTEF=1.
TMxEF bit: Mailbox empty flag, indicating that the data transmission is complete and the mailbox
becomes empty when TMxEF=1.
Transmit abort
The TMxCT bit is set in the CAN_TSTS register to abort the transmission of the current mailbox, detailed
as follows:
When the current transmission fails or arbitration is lost, if the automatic retransmission mode is disabled,
the tranmist mailbox become EMPTY; if the automatic retransmission mode is enbled, the tranmist
mailbox becomes SCHEDULED, the mailbox transmission then is aborted and becomes EMPTY.
When the current transmission is complete successfully, the mailbox becomes EMPTY.
19.6.6 Message reception
Register configuration
The CAN_RFIx, CAN_RFCx, CAN_RFDTLx and CAN_RFDTHx registers can be used by user
applications to obtain valid messages.
Message reception
The CAN controller boasts two FIFO with three levels to receive messages. FIFO rule is adopted. When
the message is received correctly and has passed the identifier filtering, it is regarded as a valid message
and is stored in the corresponding FIFO. The number of the received messages RFxMN[1: 0] will be
incremented by one whenever the receive FIFO receives a valid message. If a valid message is received
when RFxMN[1: 0]=3, the controller will select either to overwrite the previous messages or discard the
new incoming message through the MDRSEL bit in the CAN_MCTRL register.
In the meantime, when the user reads a frame of message and the RFxR is set in the CAN_RFx register,
one FIFO mailbox is released, and RFxMN[1: 0] bit is descremented by one in the CAN_RFx register.
Receive FIFO status
RFxMN[1: 0], RFxFF and RFxOF bits in the RFx register are used to indicate receive FIFO status.
RFxMN[1: 0]: indicates the number of valid messages stored in the FIFOx.
RFxFF: indicates that three valid messages are stroed in the FIFOx (i.e. the three
mailboxes are full), as shown in (c) of
RFxOF: indicates that a new valid message has been received while the FIFOx is full, as shown in (d)
of
