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AT32WB415
Series Reference Manual
2022.04.13
Page 50
Ver 2.00
4.3 CRM registers
These peripheral registers have to be accessed by bytes (8 bits), half words (16 bits) or words (32 bits).
Table 4-1
CRM register map and reset values
Register
Offset
Reset value
CRM_CTRL
0x000
0x0000 XX83
CRM_CFG
0x004
0x0000 0000
CRM_CLKINT
0x008
0x0000 0000
CRM_APB2RST
0x00C
0x0000 0000
CRM_APB1RST
0x010
0x0000 0000
CRM_AHBEN
0x014
0x0000 0014
CRM_APB2EN
0x018
0x0000 0000
CRM_APB1EN
0x01C
0x0000 0000
CRM_BPDC
0x020
0x0000 0000
CRM_CTRLSTS
0x024
0x0C00 0000
CRM_AHBRST
0x028
0x0000 0000
CRM_PLL
0x02C
0x0000 1F10
CRM_MISC1
0x030
0x0000 0000
CRM_OTG_EXTCTRL
0x044
0x0000 0000
CRM_MISC2
0x054
0x0000 000D
4.3.1
Clock control register (CRM_CTRL)
No-wait states, accessible by bytes, half-words or words.
Bit
Name
Reset value
Type
Description
Bit 31: 26
Reserved
0x00
resd
Kept at its default value.
Bit 25
PLLSTBL
0x0
ro
PLL clock stable
This bit is set by hardware after PLL is ready.
0: PLL clock is not ready.
1: PLL clock is ready.
Bit 24
PLLEN
0x0
rw
PLL enable
This bit is set and cleared by software. It can also be
cleared by hardware when entering Standby or Deepsleep
mode. When the PLL clock is used as the system clock,
this bit cannot be cleared.
0: PLL is OFF
1: PLL is ON.
Bit 23: 20
Reserved
0x0
resd
Kept at its default value.
Bit 19
CFDEN
0x0
rw
Clock failure detector enable
0: OFF
1: ON
Bit 18
HEXTBYPS
0x0
rw
High speed external crystal bypass
This bit can be written only if the HEXT is disabled.
0: OFF
1: ON
Bit 17
HEXTSTBL
0x0
ro
High speed external crystal stable
This bit is set by hardware after HEXT becomes stable.
0: HEXT is not ready.
1: HEXT is ready.
Bit 16
HEXTEN
0x0
rw
High speed external crystal enable
This bit is set and cleared by software. It can also be
cleared by hardware when entering Standby or Deepsleep
mode. When the HEXT clock is used as the system clock,
this bit cannot be cleared